Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

fixed point multiplier

Status
Not open for further replies.

sheikh

Advanced Member level 4
Joined
Sep 10, 2007
Messages
104
Helped
1
Reputation
2
Reaction score
1
Trophy points
1,298
Activity points
2,008
fix point multiplier

Hello Dears
Is it possible to give me a link that contains vhdl code for a 32 bit fix point multiplier ?(I mean, 32bits inputs and 32 bits output)
(also it must be synthesizable )
Regard
Mostafa
 
Last edited:

mrflibble

Advanced Member level 5
Joined
Apr 19, 2010
Messages
2,724
Helped
679
Reputation
1,360
Reaction score
651
Trophy points
1,393
Activity points
19,551
Just use an expression like "a*b".
 

TrickyDicky

Advanced Member level 5
Joined
Jun 7, 2010
Messages
7,091
Helped
2,078
Reputation
4,175
Reaction score
2,036
Trophy points
1,393
Activity points
39,386
Wow - thats also my favourite too MrFlibble.
 

sheikh

Advanced Member level 4
Joined
Sep 10, 2007
Messages
104
Helped
1
Reputation
2
Reaction score
1
Trophy points
1,298
Activity points
2,008
Ha haa:) when I read it again, I got surprised! because I forget to sent the main question. any way, Let me correct it, how can I coding the attached file just by using (*). Is there any way that the result of synthesis be same as using mux and multiplier directly. may be you say "use the "Process" "but, the result of synthesis have extera units.
Regards
Mostafa
Unit.png
 

TrickyDicky

Advanced Member level 5
Joined
Jun 7, 2010
Messages
7,091
Helped
2,078
Reputation
4,175
Reaction score
2,036
Trophy points
1,393
Activity points
39,386
This code is exactly whats in your diagram.


Code VHDL - [expand]
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
signal mult_result : unsigned(63 downto 0);
 
process(clk)
  variable mult_ip1, mult_ip2 : unsigned(31 downto 0);
begin
  if rising_edge(clk) then
    
    --Mux1
    if sel0 = '0' then mult_ip1 := ip0;
    else               mult_ip1 := ip1;
    end if;
      
    --mux2
    if sel1 = '0' then mult_ip2 := ip2;
    else               mult_ip2 := ip3;
    end if;
 
    --Multiplier and register in one line!
    if load = '1' then
      mullt_result <= mult_ip1 * mult_ip2;
    end if;
    
  end if;
end process;

 

sheikh

Advanced Member level 4
Joined
Sep 10, 2007
Messages
104
Helped
1
Reputation
2
Reaction score
1
Trophy points
1,298
Activity points
2,008
Thanks TrickyDicky
 

mrflibble

Advanced Member level 5
Joined
Apr 19, 2010
Messages
2,724
Helped
679
Reputation
1,360
Reaction score
651
Trophy points
1,393
Activity points
19,551
Wow - thats also my favourite too MrFlibble.

;-)

Indeed, and I wasn't even joking. :p Quite often you don't need to make it more complicated than that, as exemplified by your central line of code:

Code:
 mult_result <= mult_ip1 * mult_ip2; --- minus the typo of mullt_result vs mult_result ;-)
 
Last edited:
  • Like
Reactions: sheikh

    sheikh

    Points: 2
    Helpful Answer Positive Rating

sheikh

Advanced Member level 4
Joined
Sep 10, 2007
Messages
104
Helped
1
Reputation
2
Reaction score
1
Trophy points
1,298
Activity points
2,008
Thanks Dear mrflibble, I agree with you:))
 

Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Top