Fixed frequency oscillator in verilogA

jjx said:

@(initial_step)

--> initialize the variable next to be equal to

next T/2 + the start time (the start time is not necessarily 0 based on if you set the tstart parameter for the transient analysis. T = 1 / freq)

@(timer(next))

-> Once the simulator reaches next (first time this happens is at T/2 + $abstime)

invert/toggle n (from 0 to 1 or vice versa)
increment next = next + T/2, i.e., by another half a clock cycle.

(timer loop will no be entered once clock reaches next + T/2 and redo)

Let V(out) transition to vh if n is 1 or to vl if n is 0 with a risetime of 0 and delay of tt s.

Click to expand...

`include "constants.vams"
`include "disciplines.vams"

module osc (out);
output out; electrical out;
parameter real fc=1.0e+9 from (0:inf);
parameter real Vlo=0, Vhi=1;
parameter real tt=0.01/fc from (0:inf);
parameter real fmJitter=0 from [0:0.1/fc);
parameter real pmJitter=0 from [0:0.1/fc);
integer n, fmSeed, pmSeed;
real next, dT, dt;
analog begin
@(initial_step) begin
fmSeed = 286;
pmSeed = 459;
next = 0.5/fc + $realtime;
end
@(timer(next + dt)) begin
n = !n;
dT = fmJitter*$dist_normal(fmSeed,0,1);
dt = pmJitter*$dist_normal(pmSeed,0,1);
next = next + 0.5/fc + 0.707*dT;
end
V(out) <+ transition(n ? Vhi : Vlo, 0, tt);
end
endmodule

jjx said:

ok,

convergence issues are always a bit tricky to deal with.

Possibly:

You could try to soften the transition a bit by introducing rise and fall times.

Also, how do you define dt? Probably initiated to 0, I presume, but maybe set dt to something before using it in timer(next + dt) in your initial_step part.

Further on, even through next is a big number compared to dt (i assume?) but still watch out for the next + delta_time becoming negative numbers.

Also - you have in analoglib a phase-noise generator (I think?) allowing you to generate a sinusoid with a phase noise spectral density mask definition. Maybe it's easier to use if you bump into too many convergence issues.

Click to expand...