Fitter Failed--Quartus II- Version 12.0-- Total Memory Bits usage 0%, LE usage 1232%

[manoj87]

Hello,
I am trying to synthesis a 2KB Ram( with 1024 locations and 16 bit data respectively), in VHDL using Quartus 2 version 12.0 in a 32 bit windows 7 operating system.

I am getting message as flow failed, and getting error as cannot fit design, and from the report, what I understand is the tool is trying to compile the design using LE's instead of block rams. Is there any way or option that I can change in the tool, and hence use total memory bits, instead of LEs?.

Here is the report that I am getting.

Flow Status Flow Failed - Mon Feb 16 16:51:05 2015
Quartus II 32-bit Version 12.0 Build 232 07/05/2012 SP 1 SJ Web Edition
Revision Name ping_pong_buffer
Top-level Entity Name ping_pong_buffer
Family Cyclone II
Device EP2C5F256I8
Timing Models Final
Total logic elements 56,779 / 4,608 ( 1232 % )
Total combinational functions 24,009 / 4,608 ( 521 % )
Dedicated logic registers 32,826 / 4,608 ( 712 % )
Total registers 32826
Total pins 33 / 158 ( 21 % )
Total virtual pins 0
Total memory bits 0 / 119,808 ( 0 % )
Embedded Multiplier 9-bit elements 0 / 26 ( 0 % )
Total PLLs 0 / 2 ( 0 % )

HERE IS THE VHDL CODE

---

Code VHDL - [expand]
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---ping pong buffer with interrupt from fpga for node 4 with data_ip
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
 
entity ping_pong_buffer is
  port(
       wr_clk_20mhz: in std_logic;
       clk_1mhz: in std_logic;
       rd_clk_50mhz: in std_logic;
       data_ip: in std_logic_vector(15 downto 0);
       addr: in std_logic_vector(5 downto 0);
       read_en : in std_logic;
       f_rst: in std_logic;
       int_full : out std_logic;
         led : out std_logic;
       data_op: out std_logic_vector(15 downto 0));
       
end entity ping_pong_buffer;
 
 
 
 
architecture behav_ping_pong of ping_pong_buffer is
  
---instantiate edge detector
component edge_detector_1mhz is
port
    (clk_1mhz: in std_logic;
     clk_20mhz: in std_logic;
     f_rst: in std_logic;
      detect: out std_logic); 
end component edge_detector_1mhz;
 
---state declaration
type name_of_my_states is (s0,s1,s2);
signal state:name_of_my_states;
 
signal count_led : std_logic_vector(23 downto 0) := (others => '0');
signal toggle : std_logic := '1';
---memory declaration
type mem_epi_1 is array(0 to 63) of std_logic_vector(15 downto 0);
type mem_epi_2 is array(0 to 63) of std_logic_vector(15 downto 0);
 
  signal Ram_a: mem_epi_1; 
  signal Ram_b: mem_epi_2;
 
  
  signal count_a : std_logic_vector(15 downto 0) := (others => '0');
  signal count_b : std_logic_vector(15 downto 0) := (others => '0');
  signal detect_1mhz: std_logic;
  signal count_capture : std_logic_vector(2 downto 0) := (others => '0');
  signal int_full_sig: std_logic:= '0';
  signal ram_a_ram_bn: std_logic:= '0';
  
begin
  detector: edge_detector_1mhz port map(detect => detect_1mhz, clk_1mhz => clk_1mhz, clk_20mhz => wr_clk_20mhz, f_rst => f_rst);
    
 
----logic to capture data at 250ns intervals and write into the ping pong buffer
 
WRITE_PROCESS : process(wr_clk_20mhz)
      begin
            if (f_rst = '0') then
              count_capture <= (others => '0');
              state <= s0;
                  count_led <= (others => '0');
              toggle <= '0';
            
            elsif(rising_edge(wr_clk_20mhz)) then
                if count_led = x"ffffff" then
                  toggle <= not toggle;
                  count_led <= (others => '0');
               else 
                  count_led <= count_led + '1';
            end if;
            
                if(int_full_sig = '1') then
                    ram_a_ram_bn <= not ram_a_ram_bn;
            end if;
              
    case state is
        
       when s0 =>   int_full_sig <= '0';
                    if(detect_1mhz = '1') then
                          state <= s1;
                        else
                          state <= s0;
                        end if;
 
           
       when s1 =>   int_full_sig <= '0';
                    if(count_capture = X"4") then
                      count_capture <= (others => '0');
                    else
                      count_capture <= count_capture + '1';
                    
                    if(count_capture = X"2") then
                      Ram_a(conv_integer(count_a)) <= count_a;
                    
                    if(count_a = X"3F") then
                          count_a <= (others => '0');
                          int_full_sig <= '1';
                          state <= s2;
                        else
                          count_a <= count_a + 1;
                          state <= s1;
                    end if;
                    end if;
                    end if;
                             
       when s2 =>   int_full_sig <= '0';
                    if(count_capture = X"4") then
                      count_capture <= (others => '0');
                    else
                      count_capture <= count_capture + '1';
                    
                    if(count_capture = X"2") then
                      Ram_b(conv_integer(count_b)) <= x"BC5A";
                    
                    if(count_b = X"3F") then
                          count_b <= (others => '0');
                          int_full_sig <= '1';
                          state <= s1;
                        else
                          count_b <= count_b + 1;
                          state <= s2;
                    end if;
                    end if;
                    end if;
                                 
                        
            end case;
            end if;
            end process;
            
            int_full <= int_full_sig;
             led <= '1';
            
READ_PROCESS: process(rd_clk_50mhz)
              begin
                if(rising_edge(rd_clk_50mhz)) then
                  if(read_en = '0') then
                    if(ram_a_ram_bn = '1') then
                  
                      data_op <= Ram_a(conv_integer(addr));
                    else
                      data_op <= Ram_b(conv_integer(addr));
              end if;
              end if;
              end if;
            end process;
            end behav_ping_pong;

---

Thanks,
Manoj

 

[FvM]

Pay intention to the compilation warnings

Info (276014): Found 2 instances of uninferred RAM logic
Info (276007): RAM logic "Ram_a" is uninferred due to asynchronous read logic
Info (276007): RAM logic "Ram_b" is uninferred due to asynchronous read logic

Refer to the Quartus software handbook or the VHDL RAM design templates to learn about the requirements for RAM inference.

Essentially the synchronous FPGA hardware requires the address to be registered. The data output may be either registered or unregistered. Quartus doesn't automatically convert unregistered address/registered output to registered address/unregistered output, you have to do that.

The modified code below allows RAM inference witthout additional register delay, but generates latches for data_op. Modify according to your needs.

READ_PROCESS: process(rd_clk_50mhz)
              begin
                if(rising_edge(rd_clk_50mhz)) then
                  addr_s <= addr;
                end if;
                if(read_en = '0') then
                   if(ram_a_ram_bn = '1') then
                     data_op <= Ram_a(conv_integer(addr_s));
                   else
                     data_op <= Ram_b(conv_integer(addr_s));
                   end if;
                end if;
              end process;

 

[TrickyDicky]

As I have said on the altera forum - you need to regiter the read address before it is used to read values from the ram.

Also, as a beginner, I highly suggest you use the megawizard generated RAMs instead of inference until you are confident with their use.

 

[manoj87]

Pay intention to the compilation warnings

Thank you. I registered the read address, and then it worked perfect.

Regards,
Manoj