Error (14566): The Fitter cannot place 1 periphery component(s) due to conflicts with existing constraints (1 fractional PLL(s)). Fix the errors described in the submessages, and then rerun the Fitter. The Intel FPGA Knowledge Database may also contain articles with information on how to resolve this periphery placement failure. Review the errors and then visit the Knowledge Database at https://www.altera.com/support/support-resources/knowledge-base/search.html and search for this specific error message number.
Error (175020): The Fitter cannot place logic fractional PLL in region (0, 73) to (0, 81), to which it is constrained, because there are no valid locations in the region for logic of this type.
Info (14596): Information about the failing component(s):
Info (175028): The fractional PLL name(s): LVDS_RX:LVDS_RX_inst|altlvds_rx:ALTLVDS_RX_component|LVDS_RX_lvds_rx:auto_generated|pll_sclk~FRACTIONAL_PLL
Info (175013): The PLL output counter is constrained to the region (0, 73) to (0, 81) due to related logic
Info (175015): The I/O pad inFrame[0] is constrained to the location PIN_H14 due to: User Location Constraints (PIN_H14)
Info (14709): The constrained I/O pad is driven by a PLL LVDS output, which is driven by a PLL output counter, which is contained within this fractional PLL
Error (11238): The following 1 fractional PLL locations are already occupied, and the Fitter cannot merge the previously placed nodes with these instances. The nodes may have incompatible inputs or parameters.
Error (11239): Location FRACTIONALPLL_X0_Y74_N0 is already occupied by LVDS_TX:LVDS_TX_inst|altlvds_tx:ALTLVDS_TX_component|LVDS_TX_lvds_tx:auto_generated|pll_fclk~FRACTIONAL_PLL.
Info (175013): The PLL output counter is constrained to the region (0, 73) to (0, 81) due to related logic
Info (175015): The I/O pad outFrame[0] is constrained to the location PIN_A6 due to: User Location Constraints (PIN_A6)
Info (14709): The constrained I/O pad is driven by a PLL LVDS output, which is driven by a PLL output counter, which is contained within this fractional PLL
Error (12289): An error occurred while applying the periphery constraints. Review the offending constraints and rerun the Fitter.
Basically you have two options.
1. Change the design constraints file so that the "User Location Constraints" are modified such that the Fitter can place the fractional PLL in some other location (and it should also not being any functional change in the design).
2. Write a script that will tell the Fitter to place some parts of the design first and then the others. In this approach the Fitter will place the fractional PLL in the desired location and then will attempt to place and route the other parts.
set_location_assignment PIN_H15 -to rxClockIn
set_location_assignment PIN_G15 -to rxClockIn(n)
set_location_assignment PIN_C3 -to txClockOut
set_location_assignment PIN_B3 -to txClockOut(n)
Info (171003): Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time
Warning (292013): Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature.
Warning (15714): Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details
Critical Warning (169085): No exact pin location assignment(s) for 73 pins of 85 total pins. For the list of pins please refer to the I/O Assignment Warnings table in the fitter report.
Critical Warning (174073): No exact pin location assignment(s) for 1 RUP, RDN, or RZQ pins of 1 total RUP, RDN or RZQ pins
Info (174074): RUP, RDN, or RZQ pin memory_oct_rzqin not assigned to an exact location on the device
Info (184025): 4 differential I/O pins do not have complementary pins. As a result, the Fitter automatically creates the complementary pins.
Info (184026): differential I/O pin "outFrame[0]" does not have a complementary pin. As a result, the Fitter automatically creates the complementary pin "outFrame[0](n)".
Info (184026): differential I/O pin "txClockOut" does not have a complementary pin. As a result, the Fitter automatically creates the complementary pin "txClockOut(n)".
Info (184026): differential I/O pin "inFrame[0]" does not have a complementary pin. As a result, the Fitter automatically creates the complementary pin "inFrame[0](n)".
Info (184026): differential I/O pin "rxClockIn" does not have a complementary pin. As a result, the Fitter automatically creates the complementary pin "rxClockIn(n)".
Error (14566): The Fitter cannot place 1 periphery component(s) due to conflicts with existing constraints (1 fractional PLL(s)). Fix the errors described in the submessages, and then rerun the Fitter. The Intel FPGA Knowledge Database may also contain articles with information on how to resolve this periphery placement failure. Review the errors and then visit the Knowledge Database at https://www.altera.com/support/support-resources/knowledge-base/search.html and search for this specific error message number.
Error (175020): The Fitter cannot place logic fractional PLL in region (0, 73) to (0, 81), to which it is constrained, because there are no valid locations in the region for logic of this type.
Info (14596): Information about the failing component(s):
Info (175028): The fractional PLL name(s): LVDS_TX:LVDS_TX_inst|altlvds_tx:ALTLVDS_TX_component|LVDS_TX_lvds_tx:auto_generated|pll_fclk~FRACTIONAL_PLL
Error (11238): The following 1 fractional PLL locations are already occupied, and the Fitter cannot merge the previously placed nodes with these instances. The nodes may have incompatible inputs or parameters.
Error (11239): Location FRACTIONALPLL_X0_Y74_N0 is already occupied by LVDS_RX:LVDS_RX_inst|altlvds_rx:ALTLVDS_RX_component|LVDS_RX_lvds_rx:auto_generated|pll_sclk~FRACTIONAL_PLL.
Info (175013): The fractional PLL is constrained to the region (0, 31) to (0, 81) due to related logic
Info (175015): The I/O pad rxClockIn is constrained to the location PIN_H15 due to: User Location Constraints (PIN_H15)
Info (14709): The constrained I/O pad drives this fractional PLL
Info (175013): The PLL output counter is constrained to the region (0, 73) to (0, 81) due to related logic
Info (175015): The I/O pad outFrame[0] is constrained to the location PIN_A6 due to: User Location Constraints (PIN_A6)
Info (14709): The constrained I/O pad is driven by a PLL LVDS output, which is driven by a PLL output counter, which is contained within this fractional PLL
Error (12289): An error occurred while applying the periphery constraints. Review the offending constraints and rerun the Fitter.
You should map all the ports of your design to the device/fpga IO pins.Critical Warning (169085): No exact pin location assignment(s) for 73 pins of 85 total pins. For the list of pins please refer to the I/O Assignment Warnings table in the fitter report.
Critical Warning (174073): No exact pin location assignment(s) for 1 RUP, RDN, or RZQ pins of 1 total RUP, RDN or RZQ pins
Do you have a placement constraint for the PLL from previous device implementation? I do not know why the Fitter is trying to move the PLL from 0,73 to 0,81. But it seems like that due to change of device the location (0,81) is invalid. Please check if this location is really available on the target FPGA.Error (175020): The Fitter cannot place logic fractional PLL in region (0, 73) to (0, 81), to which it is constrained, because there are no valid locations in the region for logic of this type.
I tried. Those warnings of unasigned pins is because the board does not have a clock, so I have to create a QSys system and pick the clock signal from the HPS. I have runned the TCL scripts, but I can't give those signals a Pin Number manually, the "Pin Planner" does not allow me to do so.You should first fix the Critical Warnings.
You should map all the ports of your design to the device/fpga IO pins.
I don't know how to know if the location is available. On my expansion board I only have access to some pins of the banks 4A and 8A. I setted 8A as LVDS. Thanks for your tip.Do you have a placement constraint for the PLL from previous device implementation? I do not know why the Fitter is trying to move the PLL from 0,73 to 0,81. But it seems like that due to change of device the location (0,81) is invalid. Please check if this location is really available on the target FPGA.
Tip: Intel/Altera forums should be able to give you more clearer picture as to why these placement errors are occurring. Moreover you should also share your constraints file.
I will try to take a look at it. I don't know how to do it, but I will search it on the Internet.dpaul, that is one boundary of a region.
Ironlord,
The region from (0,73) to (0,81) has 9 cells (73-81) that are supposed to fit a PLL counter. I suggest looking to see if that is enough to hold the counter bits, or check if this region violates carry chain placement or some other alignment issue (e.g. Maybe it has to be aligned on even cells). Once you determine the region requirements, adjust the region size accordingly.
I'm not sure what you are saying. I tried to delete my constraints and allow the fitter to assign automatically the pins. It does the work, but my system is useless, because I need to output my pins through some particullar pins.Another option is to remove all region information from the constraints and see if it can find a valid location on it's own.
It's always better to assign pins, but the tools can usually place everything even if you don't have any I/O placement constraints. The drawback is It might do a poor job and the result might not meet timing.
I'm trying to get you to divide and conquer the problem.I'm not sure what you are saying. I tried to delete my constraints and allow the fitter to assign automatically the pins. It does the work, but my system is useless, because I need to output my pins through some particullar pins.
Thanks for your advice.I'm trying to get you to divide and conquer the problem.
Or skip all that and delete the region constraint and see if it finishes implementation (as I suspect it that the region constraint is too small to fit the PLL counter).
- You know the design won't fit.
- You don't know exactly why it won't fit.
- You haven't done anything to rule out something
- removing the constraints and letting the tools pick both the cell placement and the pins proves the design can be implemented in the part.
- adding back the pin placement (perhaps half of them) will let you know if the placed pins are to blame.
- add cell placement constraints back in one at a time.
LVDS_TX_inst : LVDS_TX PORT MAP (
tx_in => x"AA",
tx_inclock => clk100,
tx_out => outFrame,
tx_outclock => clk100_LVDS
);
I think because the OP was using a dev board so the baseline file for the board was automatically added to the project.Isn't there any tutorial/docu from Intel/Altera describing how to do custom placement?
For Xilinx tools you need to write a pre-routing TCL script which runs before the auto place and route tool algorithm runs.
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