# Fitter Error (14566): Cannot place 1 periphery component(s) due to conflicts with 1 fractional PLL

#### Ironlord

##### Member level 3
Hello mates!

I am trying to do a LVDS communication for testing purposes before the real project. The aim is to communicate via LVDS with a high-speed ADC @ 800mbps. On my test, I have used a Terasic DE10-Nano development board (which does not accomplish with the desired voltages) and it went quite well. The FPGA inside is a Cyclone V 5CSEBA6U23I7. I created a project and added the following IP Cores: LVDS_TX, LVDS_RX and PLL. Everything went right!

The basic project for testing was a loopback communication. The VHDL code sends 8-bits signals for 4 LVDS Channels through LVDS_TX. Through the switches and LEDs on the board, I can decide which channel to see represented. The LVDS_RX receives the signal, and with the PLL I create a 100Mhz clock, which I also send and receive using the GPIO pins.

As the project became bigger, I acquired another FPGA, an Enclustra Mercury PE1 with the Mercury SA2 module. It has a Cyclone V 5CSTFD6D5F31I7 FPGA. I replicated the same project, but I had some troubles.

-1st. I had to create a Platform Designer System to get a clock signal from the HPS. I decided to use a 50Mhz signal.
-2nd. The project i replicated didn't work, so after looking for the error on Google and reading the Intel/Altera forums, people suggested to use the ALTCLKCTRL megafunction. I obtained the same problem.
-3rd. Finally, i decided to create another 100MHz clock from the system, using the HPS. So I exported another clock signal and deleted the PLL module, because it wasn't needed no more. I still getting the same messages on the fitter.

I don't know what I am doing wrong or what should I do. On the Enclustra I am using the FMC connector to get the signals, and I bought the expansion board Terasic F2G to convert those hard to reach pins into GPIO pins. I only have access to the banks 4A and 8A. I write on the following paragraph the error messages:

Code:
Error (14566): The Fitter cannot place 1 periphery component(s) due to conflicts with existing constraints (1 fractional PLL(s)). Fix the errors described in the submessages, and then rerun the Fitter. The Intel FPGA Knowledge Database may also contain articles with information on how to resolve this periphery placement failure. Review the errors and then visit the Knowledge Database at https://www.altera.com/support/support-resources/knowledge-base/search.html and search for this specific error message number.
Error (175020): The Fitter cannot place logic fractional PLL in region (0, 73) to (0, 81), to which it is constrained, because there are no valid locations in the region for logic of this type.
Info (14596): Information about the failing component(s):
Info (175028): The fractional PLL name(s): LVDS_RX:LVDS_RX_inst|altlvds_rx:ALTLVDS_RX_component|LVDS_RX_lvds_rx:auto_generated|pll_sclk~FRACTIONAL_PLL
Info (175013): The PLL output counter is constrained to the region (0, 73) to (0, 81) due to related logic
Info (175015): The I/O pad inFrame[0] is constrained to the location PIN_H14 due to: User Location Constraints (PIN_H14)
Info (14709): The constrained I/O pad is driven by a PLL LVDS output, which is driven by a PLL output counter, which is contained within this fractional PLL
Error (11238): The following 1 fractional PLL locations are already occupied, and the Fitter cannot merge the previously placed nodes with these instances. The nodes may have incompatible inputs or parameters.
Error (11239): Location FRACTIONALPLL_X0_Y74_N0 is already occupied by LVDS_TX:LVDS_TX_inst|altlvds_tx:ALTLVDS_TX_component|LVDS_TX_lvds_tx:auto_generated|pll_fclk~FRACTIONAL_PLL.
Info (175013): The PLL output counter is constrained to the region (0, 73) to (0, 81) due to related logic
Info (175015): The I/O pad outFrame[0] is constrained to the location PIN_A6 due to: User Location Constraints (PIN_A6)
Info (14709): The constrained I/O pad is driven by a PLL LVDS output, which is driven by a PLL output counter, which is contained within this fractional PLL
Error (12289): An error occurred while applying the periphery constraints. Review the offending constraints and rerun the Fitter.

Could you help me with this issue? Thanks a lot in advance.

#### dpaul

Basically you have two options.
1. Change the design constraints file so that the "User Location Constraints" are modified such that the Fitter can place the fractional PLL in some other location (and it should also not being any functional change in the design).
2. Write a script that will tell the Fitter to place some parts of the design first and then the others. In this approach the Fitter will place the fractional PLL in the desired location and then will attempt to place and route the other parts.

#### Ironlord

##### Member level 3
Basically you have two options.
1. Change the design constraints file so that the "User Location Constraints" are modified such that the Fitter can place the fractional PLL in some other location (and it should also not being any functional change in the design).
2. Write a script that will tell the Fitter to place some parts of the design first and then the others. In this approach the Fitter will place the fractional PLL in the desired location and then will attempt to place and route the other parts.
Hello dpaul. Thanks for your response.

I'm not sure if I have done it right, because is the first time I found this kind of error, but I have tried to apply the proposed solution.

I runned the following Tcl Commands from the TCL console:

Code:
set_location_assignment PIN_H15 -to rxClockIn
set_location_assignment PIN_G15 -to rxClockIn(n)
set_location_assignment PIN_C3 -to txClockOut
set_location_assignment PIN_B3 -to txClockOut(n)
Those are the pins I have chosen on my design, using the pin planner before.
I have tried to compile and I receive the following messages:

Code:
Info (171003): Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time
Warning (292013): Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature.
Warning (15714): Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details
Critical Warning (169085): No exact pin location assignment(s) for 73 pins of 85 total pins. For the list of pins please refer to the I/O Assignment Warnings table in the fitter report.
Critical Warning (174073): No exact pin location assignment(s) for 1 RUP, RDN, or RZQ pins of 1 total RUP, RDN or RZQ pins
Info (174074): RUP, RDN, or RZQ pin memory_oct_rzqin not assigned to an exact location on the device
Info (184025): 4 differential I/O pins do not have complementary pins. As a result, the Fitter automatically creates the complementary pins.
Info (184026): differential I/O pin "outFrame[0]" does not have a complementary pin. As a result, the Fitter automatically creates the complementary pin "outFrame[0](n)".
Info (184026): differential I/O pin "txClockOut" does not have a complementary pin. As a result, the Fitter automatically creates the complementary pin "txClockOut(n)".
Info (184026): differential I/O pin "inFrame[0]" does not have a complementary pin. As a result, the Fitter automatically creates the complementary pin "inFrame[0](n)".
Info (184026): differential I/O pin "rxClockIn" does not have a complementary pin. As a result, the Fitter automatically creates the complementary pin "rxClockIn(n)".
Error (14566): The Fitter cannot place 1 periphery component(s) due to conflicts with existing constraints (1 fractional PLL(s)). Fix the errors described in the submessages, and then rerun the Fitter. The Intel FPGA Knowledge Database may also contain articles with information on how to resolve this periphery placement failure. Review the errors and then visit the Knowledge Database at https://www.altera.com/support/support-resources/knowledge-base/search.html and search for this specific error message number.
Error (175020): The Fitter cannot place logic fractional PLL in region (0, 73) to (0, 81), to which it is constrained, because there are no valid locations in the region for logic of this type.
Info (14596): Information about the failing component(s):
Info (175028): The fractional PLL name(s): LVDS_TX:LVDS_TX_inst|altlvds_tx:ALTLVDS_TX_component|LVDS_TX_lvds_tx:auto_generated|pll_fclk~FRACTIONAL_PLL
Error (11238): The following 1 fractional PLL locations are already occupied, and the Fitter cannot merge the previously placed nodes with these instances. The nodes may have incompatible inputs or parameters.
Error (11239): Location FRACTIONALPLL_X0_Y74_N0 is already occupied by LVDS_RX:LVDS_RX_inst|altlvds_rx:ALTLVDS_RX_component|LVDS_RX_lvds_rx:auto_generated|pll_sclk~FRACTIONAL_PLL.
Info (175013): The fractional PLL is constrained to the region (0, 31) to (0, 81) due to related logic
Info (175015): The I/O pad rxClockIn is constrained to the location PIN_H15 due to: User Location Constraints (PIN_H15)
Info (14709): The constrained I/O pad drives this fractional PLL
Info (175013): The PLL output counter is constrained to the region (0, 73) to (0, 81) due to related logic
Info (175015): The I/O pad outFrame[0] is constrained to the location PIN_A6 due to: User Location Constraints (PIN_A6)
Info (14709): The constrained I/O pad is driven by a PLL LVDS output, which is driven by a PLL output counter, which is contained within this fractional PLL
Error (12289): An error occurred while applying the periphery constraints. Review the offending constraints and rerun the Fitter.

#### dpaul

You should first fix the Critical Warnings.
Critical Warning (169085): No exact pin location assignment(s) for 73 pins of 85 total pins. For the list of pins please refer to the I/O Assignment Warnings table in the fitter report.
Critical Warning (174073): No exact pin location assignment(s) for 1 RUP, RDN, or RZQ pins of 1 total RUP, RDN or RZQ pins
You should map all the ports of your design to the device/fpga IO pins.

Error (175020): The Fitter cannot place logic fractional PLL in region (0, 73) to (0, 81), to which it is constrained, because there are no valid locations in the region for logic of this type.
Do you have a placement constraint for the PLL from previous device implementation? I do not know why the Fitter is trying to move the PLL from 0,73 to 0,81. But it seems like that due to change of device the location (0,81) is invalid. Please check if this location is really available on the target FPGA.

Tip: Intel/Altera forums should be able to give you more clearer picture as to why these placement errors are occurring. Moreover you should also share your constraints file.

##### Super Moderator
Staff member
dpaul, that is one boundary of a region.

Ironlord,
The region from (0,73) to (0,81) has 9 cells (73-81) that are supposed to fit a PLL counter. I suggest looking to see if that is enough to hold the counter bits, or check if this region violates carry chain placement or some other alignment issue (e.g. Maybe it has to be aligned on even cells). Once you determine the region requirements, adjust the region size accordingly.

Another option is to remove all region information from the constraints and see if it can find a valid location on it's own.

It's always better to assign pins, but the tools can usually place everything even if you don't have any I/O placement constraints. The drawback is It might do a poor job and the result might not meet timing.

#### Ironlord

##### Member level 3
First of all, thank you for your responses and your help. I really appreciate it.

You should first fix the Critical Warnings.
You should map all the ports of your design to the device/fpga IO pins.
I tried. Those warnings of unasigned pins is because the board does not have a clock, so I have to create a QSys system and pick the clock signal from the HPS. I have runned the TCL scripts, but I can't give those signals a Pin Number manually, the "Pin Planner" does not allow me to do so.

Do you have a placement constraint for the PLL from previous device implementation? I do not know why the Fitter is trying to move the PLL from 0,73 to 0,81. But it seems like that due to change of device the location (0,81) is invalid. Please check if this location is really available on the target FPGA.

Tip: Intel/Altera forums should be able to give you more clearer picture as to why these placement errors are occurring. Moreover you should also share your constraints file.
I don't know how to know if the location is available. On my expansion board I only have access to some pins of the banks 4A and 8A. I setted 8A as LVDS. Thanks for your tip.

dpaul, that is one boundary of a region.

Ironlord,
The region from (0,73) to (0,81) has 9 cells (73-81) that are supposed to fit a PLL counter. I suggest looking to see if that is enough to hold the counter bits, or check if this region violates carry chain placement or some other alignment issue (e.g. Maybe it has to be aligned on even cells). Once you determine the region requirements, adjust the region size accordingly.
I will try to take a look at it. I don't know how to do it, but I will search it on the Internet.

Another option is to remove all region information from the constraints and see if it can find a valid location on it's own.
It's always better to assign pins, but the tools can usually place everything even if you don't have any I/O placement constraints. The drawback is It might do a poor job and the result might not meet timing.
I'm not sure what you are saying. I tried to delete my constraints and allow the fitter to assign automatically the pins. It does the work, but my system is useless, because I need to output my pins through some particullar pins.

##### Super Moderator
Staff member
I'm not sure what you are saying. I tried to delete my constraints and allow the fitter to assign automatically the pins. It does the work, but my system is useless, because I need to output my pins through some particullar pins.
I'm trying to get you to divide and conquer the problem.
1. You know the design won't fit.
2. You don't know exactly why it won't fit.
3. You haven't done anything to rule out something
4. removing the constraints and letting the tools pick both the cell placement and the pins proves the design can be implemented in the part.
5. adding back the pin placement (perhaps half of them) will let you know if the placed pins are to blame.
6. add cell placement constraints back in one at a time.
Or skip all that and delete the region constraint and see if it finishes implementation (as I suspect it that the region constraint is too small to fit the PLL counter).

#### Ironlord

##### Member level 3
I'm trying to get you to divide and conquer the problem.
1. You know the design won't fit.
2. You don't know exactly why it won't fit.
3. You haven't done anything to rule out something
4. removing the constraints and letting the tools pick both the cell placement and the pins proves the design can be implemented in the part.
5. adding back the pin placement (perhaps half of them) will let you know if the placed pins are to blame.
6. add cell placement constraints back in one at a time.
Or skip all that and delete the region constraint and see if it finishes implementation (as I suspect it that the region constraint is too small to fit the PLL counter).
I'm following your steps and will try to make it fit.
Just in case, how could I delete the region constraint you mention? I mean, how can I tell to Quartus where do I want to place the PLL?
My work on VHDL has always fitted without any problems. This is the first time I'm having problems with the fitter and I realize is a part I must learn.

#### dpaul

Isn't there any tutorial/docu from Intel/Altera describing how to do custom placement?

For Xilinx tools you need to write a pre-routing TCL script which runs before the auto place and route tool algorithm runs.

#### Ironlord

##### Member level 3
I have tried to debug my problem.

1.- I created a new project and introduced the HPS to obtain a clock signal.
2.- The first test consists on blinking some leds with the clock signal and a counter. I also outputed the clock to see the signal on the oscilloscope. It works perfect.
3.- I added the PLL, this time through QSys. I do so through a 50Mhz signal to generate a 100Mhz clock.

I outputed the clk_100 signal and it works, I can see it on the oscilloscope.
4.- The next step was changing the pin output to LVDS instead of Standard 2.5V. It also works, i have the positive and the complementary negative signal.
5.- Here is where I still stuck. I added the ALTLVDS_TX module, in order to send a signal. The instance is on the following code:
Code:
LVDS_TX_inst : LVDS_TX PORT MAP (
tx_in             => x"AA",
tx_inclock    => clk100,
tx_out         => outFrame,
tx_outclock    => clk100_LVDS
);
As you see, I use the same generated clk (which output clk_100_clk is assigned to the signal clk100: clk_100_clk => clk100).

Well, when I do so, I have the same problem I mentioned on my fisrt post. I don't know what it's happening.

I can't assign the HPS pins manually, if I try, the following message appears:

The outframe is blank because I deleted the value. I wanted to test if auto assignation solved the problem, but it didn't. (The columns names, which are hidden are "Pin Location" and "Fitter Location". As you see, the fitter decided that PIN_D27 was OK for memory_oct_rzqin, but I can't assign that value manually).

I have tried to use the chip planner, but it doesn't seem to be usefull for my porpose, or it's me who doesn't know how to use it.
I don't know what more can I do.

#### Ironlord

##### Member level 3
Update:

I have made a new project. The HPS was deleted, my idea now was to use an external clock. To do so, I thought using another FPGA, generate a 50Mhz clock and connect it to an input pin.

Well, the design has been implemented, and I added the PLL (to convert the 50Mhz input clock into 100Mhz) and the ALTLVDS_TX mega function. I assigned the pins to each component. In fact there are only 3 signals (EXT_CLK, OUT_TX_CLK and Outframe).
-OUT_TX_CLK is the LVDS Clock signal, so it has also the complementary.
-Outframe is the LVDS message I send, it also has its complementary signal.

I still have the same problem, I can't place the PLL. As yesterday, I also tried to follow this instructions to place manually the PLL, but it was impossible to me: https://www.intel.com/content/www/u.../knowledge-base/solutions/rd08092011_447.html

Finally, I decided to just assign those signals the IO_BANKs instead of the signal, just in case the automatic fitter could do it's magic, but neither this worked.

Do you have more ideas I can try? Thanks in advance.

#### Akanimo

Isn't there any tutorial/docu from Intel/Altera describing how to do custom placement?

For Xilinx tools you need to write a pre-routing TCL script which runs before the auto place and route tool algorithm runs.
I think because the OP was using a dev board so the baseline file for the board was automatically added to the project.

With that baseline file, you can't reassign the IC pins as they have already been assigned. If so, one solution to this is to change the names of your ports to the node names for those pins as listed in Pin Planner. Another solution is to remove the baseline file from your project and then assign the pins manually.

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#### dpaul

I am a Xilinx guy, not familiar with Intel FPGAs.

Another solution is to remove the baseline file from your project and then assign the pins manually.
If it is true, then this is a better solution! One just writes a constrain file and in that file the DUT ports are assigned to FPGA pins using placement constraints.

#### Ironlord

##### Member level 3
The problem is I am not using a baseline file, I created a new project from zero.
I can do other kinf of staff with the FPGA, but the LVDS communication is being imposible to do.
My FMC connector only has pins on the banks 4A and 8A. Whenever I assign one of those pins to the LVDS_TX it fails the fitter, no matter if I choose a pin location or just let Quartus pick the pin it likes the most from these banks.

I have seen that when I allow Quartus fit without any constraints, it compiles without troubles, but the problem is that the pins it is assigning are not accesible on my development board (Enclustra PE-1). I have access to some pins of the banks 5A and 5B too, they are GPIO but, although is not the best solution, I could deal with it. I have tried to use that banks, and the same problem happens.

##### Super Moderator
Staff member
Are you sure the pins in those banks support the features you are using?

I don't use Intel/Altera part much so I don't know if they have the same kinds of restrictions I've seen in Xilinx parts or other vendors parts. It's seeming more and more likely that whatever primitives it's complaining about don't exist for the banks you are trying to use and the design won't place on those banks.

I would bring up whatever tools Quartus has to show you the actual placement and layout of the implemented design and look at a design that fits when there are no constraints and see what resources it is using. Then look if any of those same resources exist for the banks it won't allow placement on.

#### Akanimo

Do you have a schematic diagram or a list of pins and where they're connected to on the board?

#### FvM

##### Super Moderator
Staff member
As Cyclone 10 device handbook clearly states, dedicated LVDS TX is only available on left and right banks (1,2,5,6).

Cyclone V has dedicated LVDS TX also in top and bottom banks, but there are restrictions in PLL usage.

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#### Akanimo

Also, a pin that is already used on the board cannot be reassigned for another usage.
--- Updated ---

Last edited:

#### FvM

##### Super Moderator
Staff member
Would you mind to tell which exact FPGA you are using? Mentioned Enclustra PE-1 is apparently a FPGA independent base board which can be equipped with different FPGA modules.

The error message in post #1 and #3 reports a PLL conflict, the fractional PLL that is required for LVDS IO in the respective bank is already used for a different purpose and can't be merged, usually due to an incompatible input clock source and/or frequency. Check what the other PLL usage is and possibly overthink your clocking scheme.