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first order sigma delta ADC

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dawson

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have anyone done any simulation of the DSM . here is my design.. but my output seems to be inverted.. anyone know if im doing anything wrong or can explain to me why my waveform is inverted.
analog simulation design1.jpg

my output bit steam when input at Vmax there should be more 1s at the top however my waveform stated otherwise.

analog simulation design1 waveform.jpg

my design is a 1st order SDM..
 

monsoon

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Waveform is inverted because the integrating stage is inverting. You can add another inverting stage after the integrator, or tak Qbar as the output.
 
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dawson

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thanks for the prompt reply. but when i design my functional block design using matlab-simulink i dont need to invert my signal after the integrator. i've tried inserting an inverter after my integrator but it doesnt work. i can only invert my Q or use Q bar for as my output. But i still dont understand why my analog simulation is inverted when my integrator suppose to be taking the difference of the analog input and the feedback.
regards,
dawason
 
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monsoon

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Matlab-simulink implements the integrator as k1/s for some constant k1. But in your case, the transfer function from Vin to Vint is -1/R1C1s.
 
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dawson

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thanks for your clarification.
 

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