LukeHawk
Newbie level 1
Hey, sorry to be a hassle. I'm pretty new to VHDL and was wondering if anybody out there could help me with a problem.
I need to code a finite state machine that:
> Receives a transmit signal that tells the state machine to start (to make load high.. see below)
> sends a load signal to a shift register (already coded) that tells the shift register to load the input data.
>send a '0' to the receiver (not coded by me) to tell it to expect data 'Start bit'
>sends an enable signal to the shift register to tell it to pass the input data into the state machine serially.
>pass through 8 bits of data out of the transmitter and into the receiver
>Send a Parity bit (parity error checked in the receiver, not transmitter)
>Send a '1' to tell the receiver all the data is through 'Stop bit'
Now I did what i thought was correct... and there arent any errors in the code... but in the simulation, my output remains as hatches.. which makes me think there is a large flaw in my logic somewhere. Can somebody help me spot it? Here is my code:
NEVERMIND PROBLEM SOLVED SORT OF
I need to code a finite state machine that:
> Receives a transmit signal that tells the state machine to start (to make load high.. see below)
> sends a load signal to a shift register (already coded) that tells the shift register to load the input data.
>send a '0' to the receiver (not coded by me) to tell it to expect data 'Start bit'
>sends an enable signal to the shift register to tell it to pass the input data into the state machine serially.
>pass through 8 bits of data out of the transmitter and into the receiver
>Send a Parity bit (parity error checked in the receiver, not transmitter)
>Send a '1' to tell the receiver all the data is through 'Stop bit'
Now I did what i thought was correct... and there arent any errors in the code... but in the simulation, my output remains as hatches.. which makes me think there is a large flaw in my logic somewhere. Can somebody help me spot it? Here is my code:
NEVERMIND PROBLEM SOLVED SORT OF
