imbichie
Full Member level 6
HI Friends,
I am using VHDL for coding. Now i need to compare two files, means the input file and the output file after the simulation. So is there any method to compare two files in the Modelsim simulation.
Means i need to automate the comparison in the Main Testbench or in the *.do file (Modelsim's do file)
I am using VHDL for coding. Now i need to compare two files, means the input file and the output file after the simulation. So is there any method to compare two files in the Modelsim simulation.
Means i need to automate the comparison in the Main Testbench or in the *.do file (Modelsim's do file)