File comparison in Modelsim simulation using VHDL

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imbichie

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HI Friends,

I am using VHDL for coding. Now i need to compare two files, means the input file and the output file after the simulation. So is there any method to compare two files in the Modelsim simulation.

Means i need to automate the comparison in the Main Testbench or in the *.do file (Modelsim's do file)
 

you can easily read text files in VHDL using the textio package. Given you say you have an input file and output file, Im guessing you already know how to use them. Simply write a function that compares two files.
 

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