fifo memory initialization

stanford · Jul 6, 2018

Is below correct for initializing fifo and is this synthesizable?

Code:

logic [4:0] wptr;
logic [7:0] mem [15:0];
genvar i;

always_ff @(posedge wclk or negedge wrst)
	if (!wrst)
		for (i=0;i<16;i=i+1)
			mem[i] <= '0;
	else if (winc && !full)
		mem[wptr[3:0]] <= wdata[7:0];

ThisIsNotSam · Jul 7, 2018

stanford said:
Is below correct for initializing fifo and is this synthesizable?

Code:

logic [4:0] wptr; logic [7:0] mem [15:0]; genvar i; always_ff @(posedge wclk or negedge wrst) if (!wrst) for (i=0;i<16;i=i+1) mem[i] <= '0; else if (winc && !full) mem[wptr[3:0]] <= wdata[7:0];

This will generate a flop-based FIFO in which every flop has an async reset input. It's fine for a small size, but for larger FIFOs you probably want SRAM.

FvM · Jul 7, 2018

Power-on reset or initialization of BRAM is for free, if you want to perform an arbitrary reset, it must be coded sequentially, one memory cell per clock cycle.

ThisIsNotSam · Jul 7, 2018

FvM said:
Power-on reset or initialization of BRAM is for free, if you want to perform an arbitrary reset, it must be coded sequentially, one memory cell per clock cycle.

But but... this is ASIC.

fifo memory initialization

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fifo memory initialization

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