Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

FIFO depth using in clock domain crossing

Status
Not open for further replies.

nemolee

Full Member level 3
Joined
Dec 28, 2004
Messages
155
Helped
3
Reputation
6
Reaction score
1
Trophy points
1,298
Activity points
1,467
clock domain crossing fifo

As we know, we have to use FIFO architecture in clock domain crossing. In order to reduce the die size, how depth in FIFO size become a good learning course.
Does anyone know if there is a formula to calculate the FIFO depth good enough for us?
Thanks.
 

fifo depth

i want to know too
 

how to calculate fifo depth

if the two clock has no relationship, minimum depth is 4 words, you may also see
some design is 3 words, but it is special design, not for general case
 

clock domain crossing

it is design dependent. you should evaluate the preformance requirement. it there is not special conditon on latency, use the min size.
 

how to determine fifo size

A minimum depth of 4 in case of you r using quadrature flag, however if u r using extra bit in counters u can implement 3 word deep fifo, less than this is hardly do-able
 

fifo clock domains

Hi, nemolee

As I know, you can use the "Queueing Theory" to calculate the depth of FIFO. You can find this theory in many mathematical books.

Good Luck
 

fifo depth calculation

The smaller fifo depth, the better.

if it is better is up to your design's requirement.



nemolee said:
As we know, we have to use FIFO architecture in clock domain crossing. In order to reduce the die size, how depth in FIFO size become a good learning course.
Does anyone know if there is a formula to calculate the FIFO depth good enough for us?
Thanks.
 

fifo depth

depth=3 will slightly impact read register hold-off time.
 

queuing theory fifo design

zyphor said:
if the two clock has no relationship, minimum depth is 4 words,
if the two clock have some relationship, the depth?
for example, the write clock is 2 times of the read clock
 

fifo clock crossing

Please specify your two clock domain. i don't believe there exist a general purpose formula on FIFO depth.

PS, I saw some paper use "Queueing Theory" on this. i believe it can be helpful
 

how to find fifo depth

Say clock frequency in A domain is 100M, B is 80M. The time in the data transition process from A to B is 800ns.
In the period, 80 bytes are sent in A domain. The B domain can only receive 64 bytes. So the depth of FIFO(byte-wide) is 16.
 

Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top