As we know, we have to use FIFO architecture in clock domain crossing. In order to reduce the die size, how depth in FIFO size become a good learning course.
Does anyone know if there is a formula to calculate the FIFO depth good enough for us?
Thanks.
if the two clock has no relationship, minimum depth is 4 words, you may also see
some design is 3 words, but it is special design, not for general case
A minimum depth of 4 in case of you r using quadrature flag, however if u r using extra bit in counters u can implement 3 word deep fifo, less than this is hardly do-able
if it is better is up to your design's requirement.
nemolee said:
As we know, we have to use FIFO architecture in clock domain crossing. In order to reduce the die size, how depth in FIFO size become a good learning course.
Does anyone know if there is a formula to calculate the FIFO depth good enough for us?
Thanks.
Say clock frequency in A domain is 100M, B is 80M. The time in the data transition process from A to B is 800ns.
In the period, 80 bytes are sent in A domain. The B domain can only receive 64 bytes. So the depth of FIFO(byte-wide) is 16.