Hmmm, really ?Hi
Ltostinxlation : I have provided the data OUTPUT rate FROM clock domain A as 10 MHz. and data entry rate at clock domain B as 5MHz. SO the problem is complete.
Because the pointer sequence 000 -> 001 -> 010 -> 011 -> .... may end up in 000 -> 001 -> 011 ... due to the clock skew.Why write and read pointers of FIFO are passed to the other side using gray code during clock domain crossing?
It is complicated because A can't stop sending data if needed. How will you do this in this case? PLease elaborate. Can you guide to me a general procedure of deciding FIFO depth?
Hi
The grey coding is for crossing the counter output safely from write clock domain to read clock domain or vice versa. Is not it?
Sequential code 00 -> 01 -> 10 -> 11 -> 00 -> ...
Gray code 00 -> 01 -> 11 -> 10 -> 00 -> ..
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