$fgets problem (SystemVerilog)

[zoex666]

Hi evrybody, this is my first post. I'm newbye in Systemverilog. The following code doesn't work:

---

Code Verilog - [expand]
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module files_io();
    
  initial begin
    int fileid = $fopen("text.txt");
    if(!fileid) $display("ERROR: CAN NOT OPEN THE FILE!");
    
    while(!$feof(fileid)) begin
      string line;
      if($fgets(line,fileid))  
        $display(line);
    end
    
    $fclose(fileid);
  
  end
endmodule

---

The compilation is ok, but when I run it I get the following errors:
# ** Error: (vsim-PLI-3084) C:/Users/../files_io.sv(8): $feof : Argument 1 is not a valid file descriptor.
# Region: /files_io
# ** Error: (vsim-PLI-3084) C:/Users/../files_io.sv(10): $fgets : Argument 2 is not a valid file descriptor.

Thanks in advance for you attention.

 

[knfl]

Hi,

Did you find solution to this problem?
I am having this problem and cannot find the source of it. Also tried to search in various forums but could not find explanation.

would appreciate anybody's help

Thanks

 

[mrflibble]

Usually this is because of wrong filename combined with not checking the $fopen function return value properly. Quick test: use a full path for the filename and see if it fixes things. If fixed: congrats, you now know that you should check the $fopen results in the future. If not fixed: post your code.

 

[knfl]

Hi mrflibble,

Thanks for the hint.
the part of the code that was triggering the error is:

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always @(posedge r_hclk) begin
   if (clk_rst_file_h != 0) begin
         if (i_start == 1'b1) begin
            r_done = 1'b0;
            read_line = 1'b1;
         end
         else begin
            if (r_done_tmp == 1'b1) read_line = 1'b0;
         end
         
         if ($feof(clk_rst_file_h) == 0) begin
            
           if (cnt == 0) begin
             r_done = r_done_tmp;
             if (read_line == 1'b1) begin
               ch = $fgetc (clk_rst_file_h);
               if ((ch == "-") || (ch == "/") || (ch == "#") || (ch == 8'hFF))  begin
                  input_file_status = $ungetc(ch, clk_rst_file_h);
                  input_file_status = $fgets(line_str, clk_rst_file_h);
               end

---

The error I was getting is

$feof : Argument 1 is not a valid file descriptor.
$fgets : Argument 2 is not a valid file descriptor.

The problem is that the comment line length in the input file exceeded the "line_str" register size. After fixing this problem, I do not get the errors anymore

Thanks again

 

[mrflibble]

Thanks for the followup. That error message is rather misleading... Especially if you get it in that specific order for the above code. As in first the $feof error.

Anyways, do you check on the value of that input_file_status return value somewhere? ;-)

 

[knfl]

No, I am not checking the "input_file_status" value, maybe I should. But if I checked it, would the value indicate that there is an error in the comment line length?

 

[mrflibble]

Well, according to TFM:


17.2.4.2 Reading a line at a time

For example:

---

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integer code ;
code = $fgets ( str, fd );

---

reads characters from the file specified by fd into the reg str until str is filled, or a newline character is
read and transferred to str, or an EOF condition is encountered. If str is not an integral number of bytes in
length, the most significant partial byte is not used in order to determine the size.

If an error occurs reading from the file, then code is set to zero. Otherwise, the number of characters read is
returned in code. Applications can call $ferror to determine the cause of the most recent error (see 17.2.7).


So, you could check the return code, and then where needed use the $ferror function for fun and profit.

 

[knfl]

Thanks mrflibble, another helpful hint, much appreciated.
Excuse my lack of experience, but what is TFM that you are referring to?

 

[mrflibble]

The Fine Manual here is the IEEE 1364-2005 standard. Point your favorite search engine in the direction of "IEEE Standard for Verilog Hardware Description Language" for even more fun and profit. The fun being working verilog without (too many) "wtf is going on around here?" moments and the profit being your saved time. ;-)

 

[dave_59]

The IEEE 1800-2012 LRM is the latest and is freely available: https://go.mentor.com/get-1800

 

[mrflibble]

And to think yesterday I went looking specifically for the ieee get flavor of 1364-2005, because that's the one I got that snippet from. But now I notice that the OP actually does use SV instead of boring old verilog. Doh! In which case, yes by all means ignore my old suggestion and use the .