feedback fulladder design in verilog

[gstekboy]

Is it possible to design Iterative fulladder in verilog?
{cout,s}=a+b+cin;
A & B are input of fulladder ,cout & s are output of fulladder, each clock edge I want to input a &b but cin must be previous value of s.

module fulladder(cout,s,a,b,rst);
input a,b,rst;
output cout,s;
inout cin;
//always @(rst)


xor x1(s1,a,b);
xor x2(s,s1,cin);
and a1(c1,s1,cin);
and a2(c2,a,b);
or o1(cin,c1,c2);
assign cout=cin;


endmodule

Not working above code!!

 

[artmalik]

This is a combinational full adder as there is no reference to clock. I am not sure what are you doing with the rst pin.
The idea of doing an addition is combinational which has to complete within a clock cycle. But then the clock cycle will be very long as in case of ripple-carry addition. to make things faster you will have to put registers so the things are done in parallel rather than sequentially. Like you generate partial products and store in a flop to make things faster.

You can see a multiplier design in text books which can be implemented as a slow single block or pipeline based where you can do one addition per cycle.

 

[sharath666]

This circuit definitely has to be clocked. Else the tool reports it as a combi loop.
You can have a 2:1 mux before giving the 3rd input to the adder. The flop must be in the path from the output to back to Cin while the adder should be combinational logic.