Feasible to do this application in Coolrunner II(XC2C256)(TQ144)

[prakashvenugopal]

Hi,

Please refer the attachment and let me know this application requirement is feasible to do in Coolrunner II (XC2C256)(TQ144 package).

256x8 --> 6 Nos of RAMs -- Input RAMs
1536x8 --> 1 No of RAM -- Output RAM

I have to read the Digital values from the ADC and store it in the RAM (Each 256x8) and send the data to the PC through output RAM

Will it be feasible with coolrunner II (XC2C256). Please let me know.


Regards,
V. Prakash

View attachment Application_Requirement_in_CPLD.doc

 

[Marcel Majoor]

If I look at the datasheet, the XC2C256 has 256 macrocells. Each cell has 1 register. This basically means that no more than 256 'bits' can be stored (and this is when using no other logic whatsoever).

Hint: Just install WebPack ISE, create a project using the XC2C256 with some signals and code, and you will see if something will fit or not.

 

[prakashvenugopal]

Hi,

Thanks for your reply. If each cell has 1 register. Totally 256 macrocell are there. so, only one
256x8 RAM will be supported.? 256 is the bytes? that is we can store 00 to FF address with the data 00 to FF?

Thanks,
V. Prakash

 

[mrflibble]

Going by what Marcel Majoor just wrote, then no...

256 bits, so only 32 bytes, i,e a 32x8 RAM.

And when in doubt, you can always read the datasheet.

 

[prakashvenugopal]

Hi Mr.fibble,

Thanks. can i know where is the given in the datasheet. I am attaching the datasheet for coolrunner II XC2C256 series. Please let me know where they given this memory details.

thanks,
V. Prakash

 

[mrflibble]

General list of resources:
CoolRunner-II Data Sheets

And this one specifically:
https://www.xilinx.com/support/documentation/data_sheets/ds090.pdf

See page 5, figure 3 for an overview of the macrocell. The device you mention has 256 macrocells, so 256 registers.

 

[lucbra]

What are you actually intending to do?
Use this Coolrunner CPLD to drive a RAM that stores the values of the ADC? Or store the values of the ADC in the CPLD itself?

In the latter case (store the values in the CPLD) it's a waste of nice resources, and you only have 256 registers in the CPLD - that's it!

Typically a CPLD (like the Coolrunner) is intended for control applications (like providing the control signals W/R, CE, CS, ...) to a RAM, .... Of course there are always exceptions..

Maybe you can start with describing what your intentions are.

 

[prakashvenugopal]

Hi,

I have to store the value of ADC in CPLD. I have to implement that 256 x8 ram in cpld. If CPLD, wont support this much ram. Can i go for FPGA? In FPGA, we can do this application requirement comfortably? Please let me know.

Regards,
V. Prakash

 

[lucbra]

You have two options:
- change your device to an FPGA (and use the internal memory blocks as storage). Most FPGA's have block RAM of 9Kbit or 18Kbit. So you'll be implementing this function quite easily.
- a couple of 'so-called' CPLDs have memory on board. MAX2 (Altera) and MACHXO (Lattice) have block RAM on board that you can use as storage.

Any of these options are OK.

Do you need to physically implement? I mean, do you need to build a PCB, or is it a study case? There are quite some vendors that can help you out with a demonstrator or development board that have this functionality on board (ADC + FPGA)

Regards

 

[treqer]

- CPLDs have memory on board. MAX2 (Altera)

max 2 not have ram! it have slow and a small number of write cycles flash

 

[prakashvenugopal]

Hi,

Thanks. I will go with Xilinx FPGA itself. what FPGA series will suit my application?

18kbits = 18000bits /8 = 2250 bytes of Ram

My application required ram is 6 Nos of Input ram 256x8 = 1536 bytes of ram
1 No of output ram 1536x8 = 1536 bytes of ram

totally 3072 bytes of ram should be used for my application.

3072 x 8 = 24,576 bits rounding to 30Kbits of Bram.

Can you please suggest me what series of xilinx FPGA will suit my application.?
Please let me know.



Thanks,
V. Prakash

 

[mrflibble]

Given the lack of any further specs (sample rate etc), a spartan 3 will probably do.

 

[prakashvenugopal]

Hi,

I am planning to use 16Mhz as the base oscillator. It will sufficent for my application. I am planning to use spartan 3A series
XC3S50A for this application. Can you choose this FPGA. Please let me know.

thanks,
V. Prakash

 

[mrflibble]

I am planning to use spartan 3A series XC3S50A for this application. Can you choose this FPGA.

Wut? Ambiguous query is ambiguous.

A more detailed question might help in getting you a more detailed answer.

 

[prakashvenugopal]

Hi,

Sorry. Can i choose spartan 3A XC2C50A for my application.

My application required ram is 6 Nos of Input ram 256x8 = 1536 bytes of ram
1 No of output ram 1536x8 = 1536 bytes of ram

totally 3072 bytes of ram should be used for my application.

3072 x 8 = 24,576 bits rounding to 30Kbits of Bram.

In this XC3S50A, Block ram size is 54K. so can i go for this? or anyother FPGA to choose?
Please let me know.

thanks,
V. Prakash

 

[mrflibble]

I'd say yes.

The 54K blockram you mention will be 6x a 9Kbit blockram if memory serves me right. Too lazy to check datasheets right now, but I am sure that you can find those details for yourself.

Plus there will also be some distributed ram (the slice FF's). So 100% depending on how you are going to address your ram's it will fit.

But really, if you want to know for sure what device suits your application, you can do one of 3 things:

1) pick a larger device than you think is strictly necessary, to provide some margin
2) download ISE (free), make some prototype verilog/vhdl code with these ram's etc etc, and then synthesize the design for that XC3C50A. Then you get a very good idea if it's going to fit.
3) just get the XC3C50A, and find out. I hope you like surprises! XD


Personally I'd go for option 2. But hey, you're free to choose your pain.

---------- Post added at 11:28 ---------- Previous post was at 11:11 ----------

Oh yeah, I forgot to mention.... While doing option numero 2, you can check the synthesis report to see what resources are used, and how much is left unused. This gives you a good idea if it's going to fit or not. Then after that you can go into either FPGA Editor, or PlanAhead and take a look at how it's floorplanned. This gives you an even better idea on fit vs no fit.

Hope that helps.