I'd say yes.
The 54K blockram you mention will be 6x a 9Kbit blockram if memory serves me right. Too lazy to check datasheets right now, but I am sure that you can find those details for yourself.
Plus there will also be some distributed ram (the slice FF's). So 100% depending on how you are going to address your ram's it will fit.
But really, if you want to know for sure what device suits your application, you can do one of 3 things:
1) pick a larger device than you think is strictly necessary, to provide some margin
2) download ISE (free), make some prototype verilog/vhdl code with these ram's etc etc, and then synthesize the design for that XC3C50A. Then you get a very good idea if it's going to fit.
3) just get the XC3C50A, and find out. I hope you like surprises! XD
Personally I'd go for option 2. But hey, you're free to choose your pain.
---------- Post added at 11:28 ---------- Previous post was at 11:11 ----------
Oh yeah, I forgot to mention.... While doing option numero 2, you can check the synthesis report to see what resources are used, and how much is left unused. This gives you a good idea if it's going to fit or not. Then after that you can go into either FPGA Editor, or PlanAhead and take a look at how it's floorplanned. This gives you an even better idea on fit vs no fit.
Hope that helps.