FATAL ERROR: Simulator: Fuse.cpp:209:1.133

[ayush15]

I keep getting this error in every VHDL code I make in Xilinx ISE Design Suite 14.2,even in the smallest code of AND operation of two signals.I have tried everything- searched through the internet and xilinx forums,re-installed xilinx a number of times(by trying different softwares) and much more but could not get a working solution to it. Please if anyone knows anything about this error, do suggest.

I have spent a lot of time searching for the solution, asked friends and proffesor but could not find it. So, please it is a humble request that if anyone knows even a slight thing about it,please help.

This is the error:

FATAL_ERROR:Simulator:Fuse.cpp:209:1.133 - Failed to compile one of the generated C files. Please recompile with -mt off -v 1 switch to identify which design unit failed. Process will terminate. For technical support on this issue, please open a WebCase with this project attached at https://www.xilinx.com/support.

 

[ads-ee]

did you try recompiling with the switches? You should post the results of that.

 

[ayush15]

Thanks for the reply.
Yes, I tried that also.
1. By compiling it with -v 1 switch, I get the error as:
ERROR:Simulator:702 - Can not find design unit fuse in library work located at isim/work
2. By compiling it with -mt off, I get the following error:
FATAL_ERROR:Simulator:Fuse.cpp:500:1.133 - Failed to compile generated C file isim/precompiled.exe.sim/ieee/p_2592010699.c Process will terminate. For technical support on this issue, please open a WebCase with this project attached at https://www.xilinx.com/support.
3. By combining both, I get the same error as in 1.
4. By any other thing, I get the same error.

 

[ads-ee]

you say that a simple project with only an AND gate exhibits this problem? Have you tried a fresh install of ISE on a different machine?

I just noticed that the name of the file is Fuse.cpp. What exactly are you doing? That isn't a VHDL file extension, that looks more like a C++ file extension. ISE doesn't synthesis or simulate .cpp files. So what are you trying to accomplish. It's certainly not clear from your two posts.

Regards

 

[ayush15]

I am trying to make a vhdl code which reads a binary text file and store its contents in an array. But it gave me this error. So, I tried to make a very simple VHDL code for AND gate operation, but it gave me the same error. I tried re-installing but it didn't help.

Here is my code:

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Code VHDL - [expand]
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use STD.TEXTIO.ALL;
use IEEE.NUMERIC_STD.ALL;
 
entity binimage is
    Port ( clk : in  STD_LOGIC);
end binimage;
 
architecture Behavioral of binimage is
type abc is array(1 to 400) of bit;
signal endoffile:bit :='0';
signal data_out:abc:=(others=>'0');
signal a:integer;
signal go:bit:='0';
begin 
    process(clk)
    file file1 : text is in "C:\Users\ayush\Desktop\a.txt";
    variable n : integer:=1;
    variable i:bit;
    variable lines : line;
    begin
        if(rising_edge(clk))then
            if(not endfile(file1))then
                readline(file1,lines);
                read(lines,i);
                data_out(n) <= i;
                n:=n+1;
            else
                endoffile<='1';
                go<='1';
            end if;
        end if;
    end process;
end Behavioral;

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For your reference, this is the xilinx support page link which gives the solution to this error, but none helped.
**broken link removed**