false paths and verilog..

[ee1]

Hi all,
i have 2 questions:
1. false path - is there any method to determine if one path is a false path or it should really meet timing?
how should we decide? only after getting setup violation we should check and see if this path is maybe a false path?
or are there some paths that i should always define in all designs?

2. this question is regarding the synthesis stage - when i want to synthesis a design i should have a list of all its verilogs, right?
is there any script/way to find out a list of all verilogs regarding a specific design?

thanks!

 

[ic_qiand]

Hi there!

1.We set false path, course we want to tell tools don't care about these special path, and we can make sure these defined path have no need to check or we have other methods to check. STA tools will analyze every possible path, if we dont ask them not to do. So we have to analyze circuits to identify if the path can not met our constraints is logically impossible or a path cross asynchronous clock domains.

2.Do U mean read in a list of verilog files with scripts or to find out which verilog file is belonged to the design?

 

[ee1]

2. yes, i mean find out which verilog file is belonged to the design?

thanks!

 

[ic_qiand]

Hi, ee1!

Normally, we put a series of verilog files which related to each other in a folder, just read in all of them.
And sometimes we can find the relationship between verilog files in file head.
I have no idea about how to read in all the interrelated verilog files for different projects only with A script.

 

[ee1]

in addition to the false path question:

I would like if someone will clear the issue...
how should i work with it?
I should look at all my setup/hold violations, try to fix them and think which one doest need to meet timing?

thanks,

 

[kbulusu]

by default all paths in the design should be constrained...nothing should be left unconstrained...now you need to have good understanding of the design to figure if a path will never be exercised functionally , then you need to declare it as false path...if you dont have knowledge of the design, then its not advised to declare anything as false path..I would suggest constrain it using multi cycle path sothat the path never fails but will still be analyzed by timing analysis engine and then consult the designer or the design spec to check if thats true..another alternative soln is RTL/gate level simulations can also tell you if a path is exercised or not and so talk to your simulation folks and they can also give you a list of false paths...