Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

False Path Related Docs

Status
Not open for further replies.

spartanthewarrior

Full Member level 2
Joined
Jun 13, 2007
Messages
122
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,296
Activity points
2,142
Hi All,

Can any body Provide False Path Related Doc.

How they effect our design and How to Remove False Path

From our Design
 

A false path is a path, which exists physically on the chip, but would never be sensitised in the operation of the cihp. For example :
A output sinal A_out and input signal B_in may be connected to on I/O buffer using tristate logic, to produce the I/O pin of the chip say a port called AB_IO. The I/O buffer acts as input when say a signal 'in_sel' is high and the same I/O buffer acts as an output when 'in_sel' is low.
Now there is a path physically from A_out to AB_IO to B_in, but it will never be sensitised, in chip operation as the I/O pin at a given time can only act either as input or output.
so the path from A_out to AB_IO to B_in is a 'false_path'.

in Design Compiler there is a set_false_path command which can be used to tell it the 'false_path's of your design. Some example commands can be seen at
http://www.vlsiip.com/dc_shell

Kr,
Avi
http://www.vlsiip.com
 

Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top