Extracting VHDL netlist after place and route in soc encounter

[anjyothiswaroop]

Hey guys,
All my designs are in VHDL. I have place and routed the design using encounter. Now I want to extract the netlist and perform further analysis (functionality verification, power estimation with parasitics included). But the netlist is in verilog format and since other modules and test bench are in VHDL, I was wondering if I can extract the netlist in VHDL in encounter.

 

[rca]

I'm also originaly a VHDL designer, but I have always seen, the P&R tool generate the netlist in verilog. And the main simulator suppports both languages and can mix them.