layout2netlist
Newbie level 1
gds pin mask
Hi all,
I have several questions on the back-end side of custom cells (combinational boolean logic) design:
- First I was told it is possible to make electric verification of custom cell design from a GDS layout file. What additional information will I need in order to link the layout geometry information to the actual cell netlist ?
- I also heard about ANNOTATED GDS format. Could you point me to additional information (be it proprietary like an EDA tool or public info) ? Is it a proprietary language or a standard format ?
Thank you very much for your time, FYI my final goal is to recognize "automatically" transistor characteristics and link them to GDS layout but I don't know very much of back-end specific formats/data flows.
Hi all,
I have several questions on the back-end side of custom cells (combinational boolean logic) design:
- First I was told it is possible to make electric verification of custom cell design from a GDS layout file. What additional information will I need in order to link the layout geometry information to the actual cell netlist ?
- I also heard about ANNOTATED GDS format. Could you point me to additional information (be it proprietary like an EDA tool or public info) ? Is it a proprietary language or a standard format ?
Thank you very much for your time, FYI my final goal is to recognize "automatically" transistor characteristics and link them to GDS layout but I don't know very much of back-end specific formats/data flows.