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Extracting transistor information from layout (GDS)

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Newbie level 1
Sep 9, 2009
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gds pin mask

Hi all,

I have several questions on the back-end side of custom cells (combinational boolean logic) design:
- First I was told it is possible to make electric verification of custom cell design from a GDS layout file. What additional information will I need in order to link the layout geometry information to the actual cell netlist ?
- I also heard about ANNOTATED GDS format. Could you point me to additional information (be it proprietary like an EDA tool or public info) ? Is it a proprietary language or a standard format ?

Thank you very much for your time, FYI my final goal is to recognize "automatically" transistor characteristics and link them to GDS layout but I don't know very much of back-end specific formats/data flows.

annotated gds format

You would be looking for an "extract" or layout based
netlister. You might have to place some sort of pin
polygon or text, if you want a non-gibberish set of
net names - this all depends on how the tool recognizes
nets. There will be some body of recognition rules you
will have to write if you don't use the foundry PDK and
supported tool set. Foundry PCells ought to have some
data features that make the extract tool's life easier,
but these layers may or may not stream out with
the mask geometry data (they tend to be non-print

I know the LASI tools will do what you want, after
import of the GDS data. Electric requires some "arc"
constructs to be used which are destroyed by the
stream-out process and LVS won't work on non-
native layouts there. There may be other layout
oriented free / open source tools (like the Dolphin
suite, or Paris/MGEN) that will do it. I have not run
across any standalone tools but that means nothing.

If annotated GDS is in use, it's not in common use
(not an option in Cadence current release stream
I/O). You'd want to know if whoever made the PDK
has put in the right support for net and pin names,
in conjunction with how your eventual selection of
extract tool would recognize same.

I suggest as a start that you Google "layout netlist
SPICE" and similar keywords, if these tools I list
aren't good for your job.
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