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Hi,
I need to extract area-delay pareto curve of one verilog netlist using design compiler.
To achieve this I sweep the delay constraint using the following command:
create_clock -name clk -period "sweeping_value" [get_ports xe_clk]
and perform compile using:
compile -ungroup_all -area_effort high
Therefore for each delay constraint I get one area value.
But the problem is that sometimes the delay is much less than my constraint.
Assume, the constraint is 1.5 but the delay of the final design (after synthesis) would be 1.2 meaning that it has 0.3 positive slack.
According to me this slack can be used to reduce the area but I dont understand why design compiler does not use this timing slack to reduce area.
Is there any way to force design compiler to use this slack? In other words, when I give the constraint of 1.5 on timing, I wanna make sure that the final delay is exactly 1.5 without any positive slack.
Thanks
I need to extract area-delay pareto curve of one verilog netlist using design compiler.
To achieve this I sweep the delay constraint using the following command:
create_clock -name clk -period "sweeping_value" [get_ports xe_clk]
and perform compile using:
compile -ungroup_all -area_effort high
Therefore for each delay constraint I get one area value.
But the problem is that sometimes the delay is much less than my constraint.
Assume, the constraint is 1.5 but the delay of the final design (after synthesis) would be 1.2 meaning that it has 0.3 positive slack.
According to me this slack can be used to reduce the area but I dont understand why design compiler does not use this timing slack to reduce area.
Is there any way to force design compiler to use this slack? In other words, when I give the constraint of 1.5 on timing, I wanna make sure that the final delay is exactly 1.5 without any positive slack.
Thanks
