Oveis.Gharan
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Dear all
Salaam
Is there any way to extract Clock tree netlist from a post placed and routed design?
I want to simulate Clock tree with its parasitic RC elements which has been extracted from the design and inserted buffers in HSPICE.
I am impatiently wait to any guidance.
Thanks in advance.
Oveis
Salaam
Is there any way to extract Clock tree netlist from a post placed and routed design?
I want to simulate Clock tree with its parasitic RC elements which has been extracted from the design and inserted buffers in HSPICE.
I am impatiently wait to any guidance.
Thanks in advance.
Oveis