Explicit Applications of Mealy State Machine

[Umesh.CS]

Hi,

As we know, any FSM's can be developed using both Mealy and Moore. I was searching specific Applications where only Mealy Or Only Moore can be used.

For Example Moore are used in design of Counters, So Mealy doesn't have any role in design of Counter.

Similarly I wanted to Know, exactly in which applications Mealy are used and Moore cannot be used in such applications.

Thanks in Advance

 

[sharath666]

You can realize any kind of behaviour with either a Mealy or a Moore state machine. There are no restrictions on that. What will differ between the 2 implementations will be the number of states and the way outputs are generated.

 

[harpv]

In general, for digital design, Moore machines are preferred over Mealy machines since Mealy has a big disadvantage of a combinational path between input and output which may prove perilous when trying to meet timing.

The problem is compounded if you have multiple FSMs connected sequentially. There'll be a big combinational path starting from input of first FSM to the output of the last FSM which is not a very pleasant situation.

 

[Umesh.CS]

Hi Harpv
When you say Mealy causes problems in handling huge combinational logic. The same applies to Moore right? Because both Moore and Mealy has to execute in the same one clock cycle..right?

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[harpv]

You are right. But I'm not talking about meeting timing for the state register. I'm talking about the combinational path between input and output.

If you have just one FSM it might still be ok. But, imagine a scenario where you have cascaded multiple state machines i.e. output of one FSM going as input to the next one.

Then for a moore machine you have to meet timing only between the state registers, but for a mealy machine in addition there'll be a combinational path between the first FSM input and the last FSM output which might have to be constrained using a set_max_delay constraint etc. This will be additional work for the tool to optimize the combinational path.

Having said that, if you are going to register the output of the FSM before using it elsewhere I believe timing won't be a big headache.

Below image is a comparison between mealy and moore machines. The obvious difference you see is that there's no register breaking the timing between input and output for a mealy machine, but the moore machine the state register breaks the path.



Image source : **broken link removed**

 

[Umesh.CS]

Thanks for the Elaborating the difference.
So, I understand from the figure, In Moore you have relaxation time of 2 clock cycles to get the results. I mean in the first clock cycle the Comb+ fn logic happens, and then in the next clock cycle you decode the result and send out the Output.

In Mealy, this Extra decoding logic to get output also happens in the same clock cycle and hence adds up latency. Hence May Cause Timing Violations. Correct Me If I'm Wrong.

 

[vGoodtimes]

I've worked in EDA for a while. I've never liked this as an interview question. The better question would include Medvedev as that is what most people use (although it is a subset of Moore).

The reality is that you have coding style as deciding factor in many designs. 1-3 processes are commonly used to implement the FSM. My preference is for the 2 process FSM mainly because there are too many times when I need to use the driving signals to the state/output registers. Using 1 process means manually recreating the logic, which is error prone an unmaintainable.

The other good question is two FSM's, or one combined FSM for a given task -- especially when mutexes are used and state needs to be copied between the FSM's.