can anyone give me the operation of latch comparator....???
also how to simulate the design in cadence analog environment....
Please help me out its urgent...
If there is not PGA(program gain amplifier) adjust your input signal, the reference voltage is 1.6v. +Vref=0.8, -Vref=-0.8 maybe +Vref=Vrp-Vrn, -Vref=Vrn-Vrp.
Example you can design Vrp=0.8, Vrn=0. actual it decided by the common model voltage, usualy, common mode voltage is vdd/2.
In differential dynamc latch comparator for pipelined ADC:
Vref is decided by signal range that u want to convert in digital ...i.e in b/w -Vref to +Vref.
which is the signal range of the o/p of opamp in any one stage in PL ADC except last stage.
suppose OPAMP o/p is linearly varying b/w 0.4 V to 1.4 V...then it is 2 V peak to peak differentially.
so here differential signal is varying from -1v(0.4v-1.4v) to +1v(1.4v-0.4v).....(-Vref to +Vref) which is 2v p-p differential.
so for PL ADC, two comparator trip points will be VL(-Vref/4)=-0.25v and VH(+Vref/4)=+0.25V.i.e.
Vin <VL, o/p of comparator =00
VL<Vin<VH, o/p =01
Vin>VH, o/p = 11
where Vin is differential signal varying from -1v to +1v