Explanation of recovery time and clock reconvergence

[pradeep2323]

can anybody tell me please
recovery time,clock reconvergence

Please post material

 

[wice]

recovery removal time

recovery time is always used to describle the setup time for a clock signal to
sample a syncronus reset signal.
if you want the reset signal is sampled at this clock edge ,the reset signal
must be arrived before Trecovery and keep stable at Tremover.otherswise ,
the reset signal can't be sampled correctly.
you can get more information at this attachment.

 

[mallikmarasu]

clock reconvergence pessimism

hi wice

i did not find any attachment in this post.
if u dont mind can u post again?


regards
mallik

 

[srijesh]

recovery and removal time

Hi, Check this SDF doc. Search for removal/recovery.

 

[pronab]

recovery time removal time

did not find any attachment in this post.
if u dont mind can u post again?

 

[wice]

recovery and removal checks

soory,it seems that i can't upload attachment.
now, i would like to describle the main meaning of the materal.
recovery time and remover time are always related to a condition that a clk signal to sample a asyn signal,for example , a clk signal to sample a asyn rst signal. recovery time of clk is similar to the setup time of dff,and remover time is similar to holdup time of dff.
It is required that the asyn rst signal keep valid for a period before the clk rising edge.the period is recovery time .
It is required that the asyn rst signal keep valid for a period after the clk rising edge.the period is remover time .

Added after 4 minutes:

if recovery time or remover time are violated,the behav of circuit can be uncertain .

 

[roy_ece]

setup hold recovery removal time

hi ,
Clock Recovery /Removal Checks are a part of " Timing checks/Exceptions".

A Removal time specifies a limit for the time allowed between an active clock edge and the release of an Asynchronous control signal from the Active state.

ARecovery Time specifies a limit for the time allowed between release of an asynchronous contol signal from active state and next active clock edge.

 

[prasad_ooty]

recovery and removal timing

hi

If you know about SETUP & HOLD, then we can easily understand.

SETUP & HOLD is for synchronous input.
RECOVERY & REMOVEL is for asynchronous input.

If you want in the definition format

RECOVERY time: asynchrounous input should be stable before rising edge of the clock.

REMOVEL time: asynchronous input should be stable after rising edge of the clk.

 

[millsjam]

recovery removal timing

Clock reconvergence is a tricky issue, it is to do with variation effects on the chip. For example, process variations may mean that some wires that are supposed to be the same thickness are actually different thicknesses, temperature fluctuations and dynamic voltage variations will alter the time it takes for signals to traverse the same path.

So as an example, you may have a register to register path that shares a common clock. In the hold timing, the variation effects mean that the launch clock takes longer to reach the launching register but for the capture clock the variation makes the signal reach the capture register faster. On chip variation is incorporated in timing analysis - however there is one problem with this, if you have a common clock path then there is part of the clock path that is shared by the both launch and capture so you can't apply a variation to the common part of the clock path. Timing analysis tools take this into account - its called Clock Reconvergence Pessimism Removal