hariharan4000
Junior Member level 1
Hi
what is 'task' in verilog.
R they used only for test benches or can be used in design?
plz explain with simple verilog code eg.. a simple clock generator or sync d- flipflop.
regards
Hari
what is 'task' in verilog.
R they used only for test benches or can be used in design?
plz explain with simple verilog code eg.. a simple clock generator or sync d- flipflop.
regards
Hari