Explain me how does this circuit using CMFB work

[firsttimedesigning]

recently i am studying CMFB. i have attached file that has a circuit uses CMFB.
my question is that when Id3 and Id4 increase, why does that ouptut CM get lowered?

I think it's because that there is a set amount of current flowing into R1 and R2 from PMOS transistors. There is also a set amount of current flowing out of R1 and R2, namely Id3 + Id4. Since Id3 + Id4 increase, there is more current flowing out of R1 and R2. Therefore, the output CM level decreases. I am not sure if I am right..

One thing that i should add is Ve is the difference between Vout,cm and Vref.
Vref is connected to the negative input of the amplifier.

I also would like to know why does the feedback circuit forces Vout,cm to be equal to Vref?

 

[iamxo]

Re: CMFB

because it's negative feedback.

if it's not the case, then Ve will be very large or very small, then the circuit can not work correctly.

I think you should read Razavi's book more carefully, it is explained there.

 

[firsttimedesigning]

Re: CMFB

first of all, thank you for replying.
and yes, i know it's negative feedback. as a matter of fact, i have read that paragraph many times and thought about this for at least half hour before i decided to put this question up here.
what i dont get is how does increasing Id3 and Id4 will cause Vout1 and Vout2 to drop.
i posted my reasoning up there. please read it and to see if there is any mistake.
thank you.

 

[safwatonline]

CMFB

no common mode current goes through the resistors, so if id3 and id4 increase together then the vout1==vout2 and no current will go through the resistors.
about y the vout goes down with the current increase , u can think about it as if the out node contain a cap. with a certain charge so if u increase the current to ground the vout will decrease (cap will discharge) while if u increase the current from vdd , vout will increase (cap. will charge)