Hi,
If you happen to have Synopsys Design Compiler in-house, this might help. This example uses a 130 nm library from LSI Logic. So, yes, the library and technology matters. The example below is if Synopsys reports cell units - which it did for 130 nm LSI library.
Gate Count estimation
Things you'll need to complete this task.
1. DC area report of the design
2. Library cell unit to gates conversion factor. (This is from the ASIC vendor).
After synthesis gate count
normally, after synthesis, SCAN flops have not been inserted. So, you'll need to factor this in. Typically, the increase is 25% of noncombinational logic.
From synthesis area report, the two items that are important are
- Combinational Area (A)
- Noncombinational area (B)
1) compute estimated total gate count of design with SCAN flops by multiplying 1.25 to the Noncombinational area.
2) add result of 1 to combinational logic to get total cell area
3) convert cell area to gates by dividing result of 2 by gate factor. For LSI, it is 3.15.
4) result of 3 is gate count.
When comparing to previous design, growth percentage is determined by the following formula:
((new_gates/old_gates) - 1) x 100% = percentage increase
The equations are different for 90 nm since Synopsys area is reported in square microns - again, I believe it depends on the library. In this case, if you treated Synopsys area as cell units, your gate count would be much smaller and incorrect.