Too many externalities to predict your yield loss. And worse,
the latent / reliability-degraded tail of the population may
make it past test into the hands of your now-not-happy
customer.
It should not be difficult to hack a clamp model that has
transient simulation realism. I've been forced to do so
time and again by lame-o CAD groups who just want to
play politics (nobody was smart enough to require them
to model an ESD device as it would be used, when the
process development was planned, and now they want
to aviod any further effort... so I spent the hours to
build a TLP and pull the data and fit a hokey zener
model and lay it up inside my own private version of
the models hierarchy - and never could even get them
to take it in and maintain it, after that. So I was the
only guy at that company actually -designing- ESD
networks, as opposed to attaching things to pins and
hoping for the best.
It's all about the current loops and how the voltage
partitions around them. You can survive pin-pin
voltages > BVox(t) if the voltage is not all across
one victim. You can bet your forward diodes are
modeled reasonably and spend your efforts on the
clamp's realism. Then check GNDP-GNDA + and -
strokes with a HBM zap model, and see what you
see.