powerelec
Junior Member level 2

I am designing an IC with two separate grounds GNDA and GNDP. The two grounds are not connected to each other on chip. But they will eventually be bonded to the same pin on the package. Also there is no antiparallel diode connection between GNDA and GNDP at the chip level.
My question is regarding the ESD cells. Most of the pins have ESD cells (NMOS with gate connected to ground type) between the pin and GNDA. However one of the pins has an ESD cell from the pin to GNDP (for reasons I wont go into).
I believe this chip will be ESD safe at package level because ultimately GNDA=GNDP at the package level. But is it possible and common that the chip may sustain ESD damage at wafer level? Note - if it matters, the trimming is also wafer level.
Appreciate any advice on the matter.
Cheers
My question is regarding the ESD cells. Most of the pins have ESD cells (NMOS with gate connected to ground type) between the pin and GNDA. However one of the pins has an ESD cell from the pin to GNDP (for reasons I wont go into).
I believe this chip will be ESD safe at package level because ultimately GNDA=GNDP at the package level. But is it possible and common that the chip may sustain ESD damage at wafer level? Note - if it matters, the trimming is also wafer level.
Appreciate any advice on the matter.
Cheers