ESD cells and grounding

[powerelec]

I am designing an IC with two separate grounds GNDA and GNDP. The two grounds are not connected to each other on chip. But they will eventually be bonded to the same pin on the package. Also there is no antiparallel diode connection between GNDA and GNDP at the chip level.

My question is regarding the ESD cells. Most of the pins have ESD cells (NMOS with gate connected to ground type) between the pin and GNDA. However one of the pins has an ESD cell from the pin to GNDP (for reasons I wont go into).

I believe this chip will be ESD safe at package level because ultimately GNDA=GNDP at the package level. But is it possible and common that the chip may sustain ESD damage at wafer level? Note - if it matters, the trimming is also wafer level.

Appreciate any advice on the matter.

Cheers

 

[AMS012]

It will be safe if you can put an ESD cell between GNDA and GNDP.

 

[D.A.(Tony)Stewart]

You might consider reducing the ESD risk during processing with a resistor connecting the GNDA and GNDP, which gets shunted later in wire bonding.

 

[powerelec]

Sunnysky thanks - that is a interesting idea. I may consider that.

Just wondering also assuming I dont change anything from my original plan - do you have an estimate on how much the yield is lowered due to wafer level ESD failure?

- - - Updated - - -

Thanks AMS but it may be too late in design cycle to fit an another ESD cell (or antiparallel diodes)

 

[dick_freebird]

At 10V-ish levels you can see a lot of bare-wafer fallout.
100V-ish may still be a wire bonder, singulation, etc. issue.
Question whether your GNDA has any discharge path to
the substrate, and I'd expect the answer is "yes" unless
GNDA is only going to FET gates. In this case non-contact
charging isn't going to be a problem and only real zaps
would be. On the other hand a precision ground is one of
your fussier places to take a hit.

Eyeball what's between pad & substrate, total junction
area and MOSFET width, compare to ESD cell and get
a rough idea of relative withstand.

 

[powerelec]

Hi Dick,

Thanks, I understand your point about looking for the most likely path for ESD discharge for the one pin that is connected to GNDP and making sure that path can handle the ESD stresses.

That aside - lets assume GNDP was connected only to the gates of FETs. And I have this one pad whose ESD cell is between the pin and GNDP like I explained in the OP. In this case - what sort of yield reduction am I likely to witness as compared to having all ESD cells connected to GNDA? If it matters my chip is 10 pins. Also say we assume that all players in the wafer sorting, trimming, bonding process are using standard ESD safeguard measures.

I'm trying to figure out if the yield loss would be an extra 0.1% or would it be an extra 10%. ie. do I lose sleep over it or not

Cheers

 

[D.A.(Tony)Stewart]

https://www.google.com/url?sa=t&rct...0MWUTDnWw&sig2=mLsVnxXPObknEgaMwsld0Q&cad=rja

Some background on wafer level ESD mystery failures

 

[dick_freebird]

Too many externalities to predict your yield loss. And worse,
the latent / reliability-degraded tail of the population may
make it past test into the hands of your now-not-happy
customer.

It should not be difficult to hack a clamp model that has
transient simulation realism. I've been forced to do so
time and again by lame-o CAD groups who just want to
play politics (nobody was smart enough to require them
to model an ESD device as it would be used, when the
process development was planned, and now they want
to aviod any further effort... so I spent the hours to
build a TLP and pull the data and fit a hokey zener
model and lay it up inside my own private version of
the models hierarchy - and never could even get them
to take it in and maintain it, after that. So I was the
only guy at that company actually -designing- ESD
networks, as opposed to attaching things to pins and
hoping for the best.

It's all about the current loops and how the voltage
partitions around them. You can survive pin-pin
voltages > BVox(t) if the voltage is not all across
one victim. You can bet your forward diodes are
modeled reasonably and spend your efforts on the
clamp's realism. Then check GNDP-GNDA + and -
strokes with a HBM zap model, and see what you
see.

 

[powerelec]

Hi Dick,

Just an update - eventually I decided to connect the ESD cell to GNDA to avoid having to do the ESD analysis the way you explained.

ESD to GNDA for this particular pin means slightly more switching noise but not catastrophically so. Sadly my (tiny) company does not have a strong ESD consultant in house at the time either. I do hope to read up more on ESD so I have a larger tool-kit when I run into stuff like this in the future.

Thanks (to you and others) for the help. This is a great forum.