errors in simulating the outuput of a synchronous fifo in verilog

[theHermes]

Hi,
I have modified the code that I found on the net for my requirements.But, I realise that there are a few errors and I am unable to debug them.It would be great if you can help me with this.
my code and testbench are as follows:

module syncfifo(
clk,
rst,
read_rq,
write_rq,
rw_address,
write_data,
read_data
);
input clk;
input rst;
input read_rq;
input write_rq;
input[7:0] rw_address;
input[7:0] write_data;
output[7:0] read_data;

reg[7:0] read_data;

integer out, i;
reg [7:0] memory_ram_d [0:15];
reg [7:0] memory_ram_q [0:15];

always @(posedge clk or
negedge rst)
begin
if (rst)
begin
for (i=0;i<15; i=i+1)
memory_ram_q <= 0;
end
else
begin
for (i=0;i<15; i=i+1)
memory_ram_q <= memory_ram_d;
end
end


always @(posedge clk or negedge rst)
begin
for (i=0;i<15; i=i+1)
memory_ram_d = memory_ram_q;
if (write_rq && !read_rq)
memory_ram_d[rw_address] = write_data;
if (!write_rq && read_rq)
read_data = memory_ram_q[rw_address];
end
endmodule

//testbench

module syncfifotestbench ();
reg clk, rst;
reg read_rq;
reg write_rq;
reg[7:0] rw_address;
reg[7:0] write_data;
wire[7:0] read_data;
reg [3:0] q_cnt;
integer seed;
initial
begin
clk = 0;
forever #10 clk = ~clk;
end

initial begin
rst = 1;
# 50 rst = 0;
end

always @(posedge clk or
negedge rst)
begin
if (rst)
begin
q_cnt <= 0;
end
else
begin
if (q_cnt < 15)
begin
q_cnt <= q_cnt+1;
write_data <= $random(seed) & 'hFF;
read_rq <= 0;
write_rq <= 1;
rw_address <= q_cnt;
end
else
begin
q_cnt <= q_cnt;
write_data <= write_data;
rw_address <= $random(seed) & 'h3F;
read_rq <= 1;
write_rq <= 0;
end
end
end
syncfifo h1(clk,
rst,
read_rq,
write_rq,
rw_address,
write_data,
read_data);

endmodule


the problems that i am facing are:
1. I need to transmit 15 bytes at a time. So, I need to get 15 bytes of data at a stretch when the read-request is enabled.But, I am getting information in different time slots. where do i need to make changes to achieve the same?
2. Why is the write_data signal still show the value 11111001 when read_request signal has been enabled?(it should be xxxxxxxx right?)
3.thirdly,my first stream of information in read_data ouput is 00000000 whereas my write_data shows 10000001 as first information. does that mean i am losing some bytes while writing data?
4.finally, why do I see a few places wherein my read_data signal is xxxxxxx when read_req is high?


Kindly answer my questions, so that I will be able to proceed in my project.

Thanks for ur time and efforts.