Error when compiling with VCS

[tenso]

Ok so I was following this tutorial to do verilog simulations in iverilog.

https://iverilog.wikia.com/wiki/GTKWAVE

Both counter.v and counter_tb.v compiled fine and I was able to get the wave forms like it says with GTKWave.

Now I tried to compile the same .v files with VCS and this was the error I ended up getting.

Error-[V2KS] Verilog 2000 IEEE 1364-2000 syntax used. Please compile with +v2k
to support this construct

I did compile with +v2k option but it created a bunch of files and directories. Can anyone explain why I got this error? It doesn't seem to like that I used reg.
Also does what does the +v2k option do? I was looking for an executable that I could run with the -gui option so that I could look at the signals in DVE.

 

[ads-ee]

There were changes that added new syntax to Verilog in 2000/2001, so the switch is just telling the compiler to allow the use of 2000 (2k) syntax.

VCS has been around a long time, so I imagine the default behavior was not changed over the years so that users wouldn't have to modify any scripts to run things as they came out with new versions of the language. I'm sure to support Verilog 2005 or System Verilog requires a different command line option.

 

[tenso]

There were changes that added new syntax to Verilog in 2000/2001, so the switch is just telling the compiler to allow the use of 2000 (2k) syntax.

VCS has been around a long time, so I imagine the default behavior was not changed over the years so that users wouldn't have to modify any scripts to run things as they came out with new versions of the language. I'm sure to support Verilog 2005 or System Verilog requires a different command line option.

Yeah I tried both options , +v2k and -sverilog but it gave me some directories and files I don't know what to do with after compilation. I was hoping someone who is familiar with VCS would tell me how these options work and if compiling with them produces an executable.

 

[dpaul]

I use the option -sverilog and it does produce an executable. I don't remember doing anything special.

 

[yuhiub90]

Add -R option to your compilation. VCS will execute the simulation automatically.

 

[tenso]

Add -R option to your compilation. VCS will execute the simulation automatically.

I typed this in
vcs -R +v2k counter.v counter_tb.v


but I am getting this error.

Starting vcs inline pass...
1 module and 0 UDP read.
recompiling module test
if [ -x ../simv ]; then chmod -x ../simv; fi
g++  -o ../simv -melf_i386   -Wl,-whole-archive    -Wl,-no-whole-archive  _vcsobj_1_1.o  5NrI_d.o 5NrIB_d.o SIM_l.o     rmapats_mop.o rmapats.o      /usr/synopsys/VCS-2011.03/linux/lib/libvirsim.so /usr/synopsys/VCS-2011.03/linux/lib/librterrorinf.so /usr/synopsys/VCS-2011.03/linux/lib/libsnpsmalloc.so     /usr/synopsys/VCS-2011.03/linux/lib/libvcsnew.so /usr/synopsys/VCS-2011.03/linux/lib/libuclinative.so         /usr/synopsys/VCS-2011.03/linux/lib/vcs_save_restore_new.o /usr/synopsys/VCS-2011.03/linux/lib/ctype-stubs_32.a -ldl  -lc -lm -lpthread -ldl 
g++: error: unrecognized command line option ‘-melf_i386’
make: *** [product_timestamp] Error 1
Make exited with status 2

 

[dpaul]

Send me the source code if possible, I'll try to compile it my VCS environment.

 

[dpaul]

Tried compiling in my VCS environment and everything works smoothly. I am pasting whatever was thrown out at the command prompt.

dpaul@crest:~/rtl_work/test$ 
dpaul@crest:~/rtl_work/test$ vcs -full64  +v2k -debug_all  counter_tb.v counter.
                         Chronologic VCS (TM)
       Version I-2014.03-SP1_Full64 -- Fri Apr 17 16:13:33 2015
               Copyright (c) 1991-2014 by Synopsys Inc.
                         ALL RIGHTS RESERVED

This program is proprietary and confidential information of Synopsys Inc.
and may be used and disclosed only as authorized in a license agreement
controlling such use and disclosure.

Parsing design file 'counter_tb.v'
Parsing design file 'counter.v'
Top Level Modules:
       test
No TimeScale specified
Starting vcs inline pass...
1 module and 0 UDP read.
recompiling module test because:
        Some compilation options have been changed.
rm -f _csrc*.so amd64_scvhdl_*.so pre_vcsobj_*.so share_vcsobj_*.so
ld -shared -o .//../simv.daidir//_csrc1.so --whole-archive _vcsobj_1_1.a  --no-warchive
ld -shared -o .//../simv.daidir//_csrc0.so 5NrI_d.o 5NrIB_d.o SIM_l.o  
if [ -x ../simv ]; then chmod -x ../simv; fi
g++  -o ../simv    -Wl,-rpath-link=./ -Wl,-rpath='$ORIGIN'/simv.daidir/ -Wl,-rpaORIGIN'/simv.daidir//scsim.db.dir  _csrc1.so _csrc0.so     rmapats_mop.o rmapatsar.o           /home/shared/Synopsys/I-2014.03-SP1/amd64/lib/libzerosoft_rt_stub/home/shared/Synopsys/I-2014.03-SP1/amd64/lib/libvirsim.so /home/shared/Synopsys14.03-SP1/amd64/lib/liberrorinf.so /home/shared/Synopsys/I-2014.03-SP1/amd64/libnpsmalloc.so    /home/shared/Synopsys/I-2014.03-SP1/amd64/lib/libvcsnew.so /homeed/Synopsys/I-2014.03-SP1/amd64/lib/libuclinative.so   -Wl,-whole-archive /home/d/Synopsys/I-2014.03-SP1/amd64/lib/libvcsucli.so -Wl,-no-whole-archive          /shared/Synopsys/I-2014.03-SP1/amd64/lib/vcs_save_restore_new.o -ldl -lm  -lc -lad -ldl 
../simv up to date
CPU time: .076 seconds to compile + .044 seconds to elab + .164 seconds to link
dpaul@crest:~/rtl_work/test$ 
dpaul@crest:~/rtl_work/test$ 
dpaul@crest:~/rtl_work/test$ ./simv -gui &
[2] 16088
dpaul@crest:~/rtl_work/test$ ll
insgesamt 780
-rw-rw---- 1 dpaul dpaul    492 Apr 17 16:09 counter_tb.v
-rw-rw---- 1 dpaul dpaul    325 Apr 17 16:08 counter.v
drwxrwx--- 3 dpaul dpaul   4096 Apr 17 16:13 csrc
drwxrwx--- 2 dpaul dpaul   4096 Apr 17 16:13 DVEfiles
-rw-rw---- 1 dpaul dpaul   1334 Apr 17 16:13 inter.vpd
-rwxrwx--- 1 dpaul dpaul 773529 Apr 17 16:13 simv
drwxrwx--- 3 dpaul dpaul   4096 Apr 17 16:13 simv.daidir
-rw-rw---- 1 dpaul dpaul      0 Apr 17 16:13 ucli.key
[2]+  Fertig                  ./simv -gui
dpaul@crest:~/rtl_work/test$

I could also successfully bring up the GUI/DVE. Was not even 5 min work!

 

[tenso]

there seems to be an error when compiling that results in simv not being an executable. This is the error message I get

   Chronologic VCS (TM)
            Version E-2011.03 -- Fri Apr 17 16:12:11 2015
               Copyright (c) 1991-2011 by Synopsys Inc.
                         ALL RIGHTS RESERVED

This program is proprietary and confidential information of Synopsys Inc.
and may be used and disclosed only as authorized in a license agreement
controlling such use and disclosure.

Parsing design file 'counter_tb.v'
Parsing design file 'counter.v'
Top Level Modules:
       test
No TimeScale specified
Starting vcs inline pass...
1 module and 0 UDP read.
recompiling module test
if [ -x ../simv ]; then chmod -x ../simv; fi
g++  -o ../simv -melf_i386   -Wl,-whole-archive    -Wl,-no-whole-archive  _vcsobj_1_1.o  5NrI_d.o 5NrIB_d.o SIM_l.o     rmapats_mop.o rmapats.o      /usr/synopsys/VCS-2011.03/linux/lib/libvirsim.so /usr/synopsys/VCS-2011.03/linux/lib/librterrorinf.so /usr/synopsys/VCS-2011.03/linux/lib/libsnpsmalloc.so     /usr/synopsys/VCS-2011.03/linux/lib/libvcsnew.so /usr/synopsys/VCS-2011.03/linux/lib/libuclinative.so         /usr/synopsys/VCS-2011.03/linux/lib/vcs_save_restore_new.o /usr/synopsys/VCS-2011.03/linux/lib/ctype-stubs_32.a -ldl -lm  -lc -lpthread -ldl 
[B]g++: error: unrecognized command line option ‘-melf_i386’[/B]
make: *** [product_timestamp] Error 1
Make exited with status 2
CPU time: .268 seconds to compile + .664 seconds to elab + .248 seconds to link

I was hoping someone could point me in the right direction.

 

[dpaul]

there seems to be an error when compiling that results in simv not being an executable. This is the error message I get.

You have again not posted the entire cmd. Did you use the option -debug_all which is necessary to create a simv executable?

I was hoping someone could point me in the right direction.

Then it is time for you look into the VCS Reference Manual and see what options who need and why is it failing.
I copy-pasted the entire compilation in my post. There is nothing better I can do.

 

[tenso]

You have again not posted the entire cmd. Did you use the option -debug_all which is necessary to create a simv executable?


Then it is time for you look into the VCS Reference Manual and see what options who need and why is it failing.
I copy-pasted the entire compilation in my post. There is nothing better I can do.

yes to the bolded

here is what i ran

vcs -debug_all +v2k counter.v counter_tb.v

This is what my compilation gives me

                     Chronologic VCS (TM)
            Version E-2011.03 -- Sat Apr 18 13:31:22 2015
               Copyright (c) 1991-2011 by Synopsys Inc.
                         ALL RIGHTS RESERVED

This program is proprietary and confidential information of Synopsys Inc.
and may be used and disclosed only as authorized in a license agreement
controlling such use and disclosure.

Parsing design file 'hello_world.v'
Top Level Modules:
       hello_world
No TimeScale specified
Starting vcs inline pass...
1 module and 0 UDP read.
recompiling module hello_world
if [ -x ../simv ]; then chmod -x ../simv; fi
g++  -o ../simv -melf_i386   -Wl,-whole-archive    -Wl,-no-whole-archive  _vcsobj_1_1.o  5NrI_d.o 5NrIB_d.o SIM_l.o     rmapats_mop.o rmapats.o      /usr/synopsys/VCS-2011.03/linux/lib/libvirsim.so /usr/synopsys/VCS-2011.03/linux/lib/librterrorinf.so /usr/synopsys/VCS-2011.03/linux/lib/libsnpsmalloc.so     /usr/synopsys/VCS-2011.03/linux/lib/libvcsnew.so /usr/synopsys/VCS-2011.03/linux/lib/libuclinative.so         /usr/synopsys/VCS-2011.03/linux/lib/vcs_save_restore_new.o /usr/synopsys/VCS-2011.03/linux/lib/ctype-stubs_32.a -ldl -lm  -lc -lpthread -ldl 
[B]g++: error: unrecognized command line option ‘-melf_i386’[/B]
make: *** [product_timestamp] Error 1
Make exited with status 2
CPU time: .152 seconds to compile + .088 seconds to elab + .156 seconds to link

the bolded above is the g++ related error I am getting. It doesn't recognize the -melf_i386 option

 

[ads-ee]

Just search on the melf_386 brings up the following: https://bugzilla.redhat.com/show_bug.cgi?id=902318