Error: The signal is not driven by any source pin in the design.

[djc]

Hello all,
I am very new to FPGA development. I have Numato Uno Spartan 6 FPGA development board. I want to switch on and off the LED's on the board after 1 second. I tried to use CLK pin. Here is the code and constraint file.

module my_led(A,D,LED,CLK);

   input  A,D,CLK;    //A and D are switches
    output reg [7:0] LED;
       integer i;
    reg count=0;   
    
    always@(posedge CLK)begin
        
        count <= count+1;
        if(count==30) begin
      
        count=0;
            i=i + 1;
            if(i==1) begin
            LED = 8'b1;
            
            end
            if(i==2) begin
            LED = 8'b0;             
            i=0;
            end
        end
    end   
endmodule

This is the constraint file.

     //NET "RST_n"       IOSTANDARD = LVCMOS33 | PULLUP;
     NET "CLK"      LOC = V10 | IOSTANDARD = LVCMOS33 | PERIOD = 100MHz;
    

     NET "LED[0]"               LOC = P15  | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST ;
    NET "LED[1]"               LOC = P16  | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST ;
    NET "LED[2]"               LOC = N15  | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST ;
    NET "LED[3]"               LOC = N16  | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST ;
    NET "LED[4]"               LOC = U17  | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST ;
    NET "LED[5]"               LOC = U18  | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST ;
    NET "LED[6]"               LOC = T17  | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST ;
    NET "LED[7]"               LOC = T18  | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST ;

# Onboard LEDs

However neither clock is working.. nor LED port is working. These are the errors i am getting.

PhysDesignRules:368 - The signal <LED<0>_OBUF> is incomplete. The signal
is not driven by any source pin in the design.
And

PhysDesignRules:10 - The network <LED<0>_OBUF> is completely unrouted.

Thhse errors are there for all the 8 LED's. What changes do i have to make in the code. Plz guide me on this.

 

[dpaul]

First improve your RTL.
Inside the always block you are using blocking assignments. Your target is to design a counter which is a sequential logic element.
Use non-blocking assignments to describe the counter.
There are numerous online references and examples explaining non-blocking/blocking cases along with counter examples. Study them!

Later we can come to board level debugging and constraining your design.

 

[FvM]

count is a binary variable and can't take larger values then 1. Respectively count == 30 never happens.

 

[ads-ee]

Use non-blocking assignments (<=) in sequential always blocks i.e. always @(posedge clk).
Use blocking assignments (=) in combonational always blocks i.e. always @(*)

Also since your clock is 100 MHz in the contraints (even if the code worked, which it may not the integer i stuff will probably synthesize incorrectly from what you think it's behavior would be, it won't simulate they way you think either) you wouldn't be able to see the LED switch as you would be switching it at 300ns, which humans are incapable of seeing. Nor is the LED capable of producing any visible output at that rate.

You will need to count at a minimum from 0-24,999,999 counts (i.e. 1/4 second, which will flicker) I usually set heartbeat LEDs to 1 second.

The usage of i doesn't make a lot of sense, use the counter directly to toggle the LED output or toggle the LED directly with an if statement that checks for a count value to do LED[0] <= ~LED[0];

--- Updated Aug 27, 2020 ---

Forgot to mention the error probably exists because the use of the blocking assignments for i and LED[0], I'm not going experiment with code as I already know code like this won't work correctly and isn't worth the effort to discover the exact issue involved.

FYI, you need to look at example code like on https://www.asic-world.com/examples/verilog/index.html