ERROR: Place:293 - Mapping error in virtex 6 fpga

[Marti]

ERRORlace:293 - Mapping error in virtex 6 fpga

Hi all,

I am developing a design using Virtex 6 (XC6VLX240T-1FF1156). In this design Im cascading two inputs using DSP48 Slices. There are a total of 768 Dsp slices present out of which Im using 512 of them. In the user guide it was written that only 96 DSP Slices can be cascaded using the inputs A and B in one column. Hence the design was written in such a fashion. Currently Im getting an error at the Mapping stage as follows:

ERRORlace:293 - The following 96 components are required to be placed in a specific relative placement form. The required relative coordinates in the RPM grid (that can be seen in the FPGA Editor) are shown in brackets next to the component names. Due to placement constraints it is impossible to place the components in the required form.

When i look into the Mapping report there is a detailed analysis as follows:

Place:293 - The following 96 components are required to be placed in a specific relative placement form. The required relative coordinates in the RPM grid (that can be seen in the FPGA Editor) are shown in brackets next to the component names. Due to placement constraints it is impossible to place the components in the required form.
DSP48E1 inst1/dsp123_inst1/dsp_2inst/blk00000003/blk00000006 (0, 0)
DSP48E1 inst1/dsp123_inst1/dsp_3inst/blk00000003/blk00000006 (0, 5)
DSP48E1 inst1/dsp123_inst1/dsp_1inst/blk00000003/blk00000006 (0, -5)
DSP48E1 inst1/dsp123_inst1/dsp_6inst/blk00000003/blk00000006 (0, 20)
DSP48E1 inst1/dsp123_inst1/dsp_7inst/blk00000003/blk00000006 (0, 25)
DSP48E1 inst1/dsp123_inst1/dsp_5inst/blk00000003/blk00000006 (0, 15)
DSP...
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I have tried implementing the design with and without area grouping constraints, but with no avail. Please help!!

 

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Re: ERRORlace:293 - Mapping error in virtex 6 fpga

DSP48s as with anything else in these devices are in columns, due to other features in the die some of those columns do not span the entire device, those areas where they don't span the entire column are going to have less of this cascading feature. I imagine this is what you are seeing. The only way around this is to change the cascading to something more granular or use a bigger part that has more available resource, where the restrictions due to the those other features do not interrupt the DSP cascading.

 

[Marti]

Re: ERRORlace:293 - Mapping error in virtex 6 fpga

Ya sure....Im trying the granular method currently and i dont get to see these errors anymore. Thanx a lot adsee!!