Error of width mismatch port with DC

[haianh]

Hi all,

I have trouble with dc_shell. My design contain some small RTL module which are generated by EDA tool. They contain some connections that have mismatch between port size and connection size but do not affect to functional logic. I tested my design with QuestaSim, VCS and synthesis by Talus. Everything is ok.

But with DC, it report "Error: Width mismatch on port ...". The synthesis process still run normally, I have gate netlist but then it contains blackbox for reference module that it report width mismatch.

I can not modify all width mismatch because there are many and they are inside some generated IP by tool.

So do we have any solution for this problem? Such as some config command to accept/bypass the error of width mismatch port in dc_shell.

Thank you for any help!

 

[rca]

Normaly, there could control the level grade of report, and swap it from error type to warning type, but seriously, I prefer to fix them instead ignoring them.

 

[haianh]

Thank rca. So what dc_shell command that i can use to control it?

Because right now, my DC synthesis script can run but it return a gate netlist with blackbox and it is absolutely a wrong netlist. All my functional logic is affected by this error.

PS: Talus can synthesis normally and it return the correct netlist for me. I do not need to config any Talus command.

 

[zhanggd]

If your final target is a chip, you'd better sort it out. Otherwise, if you just focus on the design and want to make it pass the DC, you can write a wrapper where you can choose which bits to use. Warnings will be reported.

Hi all,

I have trouble with dc_shell. My design contain some small RTL module which are generated by EDA tool. They contain some connections that have mismatch between port size and connection size but do not affect to functional logic. I tested my design with QuestaSim, VCS and synthesis by Talus. Everything is ok.

But with DC, it report "Error: Width mismatch on port ...". The synthesis process still run normally, I have gate netlist but then it contains blackbox for reference module that it report width mismatch.

I can not modify all width mismatch because there are many and they are inside some generated IP by tool.

So do we have any solution for this problem? Such as some config command to accept/bypass the error of width mismatch port in dc_shell.

Thank you for any help!

 

[layowblue]

I would suggest you ask synopsys service directly, especially when other synthesis tool can successfully operate on your design. (Assuming you have a DC license)
DC is almost standard tool, and I believe there must be some solutions.

 

[haianh]

If your final target is a chip, you'd better sort it out. Otherwise, if you just focus on the design and want to make it pass the DC, you can write a wrapper where you can choose which bits to use. Warnings will be reported.

The problem that I can not write a wrapper is because of the width mismatch is from some IP modules in lower hierarchy level. These module are generated by tool and I don't have permission to modify them.

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I would suggest you ask synopsys service directly, especially when other synthesis tool can successfully operate on your design. (Assuming you have a DC license)
DC is almost standard tool, and I believe there must be some solutions.

Yes. I'm searching solution around before contact with their support. I think this problem is common and maybe someone have met it and can give some advice.