Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

error maxplus II: help me.

Status
Not open for further replies.

ktnha

Newbie level 2
Joined
Dec 8, 2009
Messages
2
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,281
Location
viet nam
Activity points
1,293
I write code with maxplus II version 10.2:
.....
architecture rtl of sys is
type regtype is array(0 to M-1) of wrdtype;
signal REG: regtype;
signal RW: std_logic_vector(1 downto 0);
begin
...
process(...)
begin
....
for j in 0 to M-1 loop
line 32: REG(j) <= (REG(j)'range => '0');
end loop;
....
end process;
...
end rtl.

when compiler, i see error:
Error: line 32: Unsupported feature error: aggregates are supported only types that map to an array of bits.
this my files:
 

Re: error: help me.

Hi,

Try to replace the for-statement with:

reg <= (others => (others => '0'));

Maybe this can be synthesized by MaxPlusII. If this does not solve your issue, can you upgrade to QuartusII software? I am pretty sure QuartusII supports both constructs.

Devas
 

error: help me.

reg <= (others =>(others => '0'));
I don't solve my issue. I must to use maxplus for my design.
please, help me.
 

Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top