ktnha
Newbie level 2
I write code with maxplus II version 10.2:
.....
architecture rtl of sys is
type regtype is array(0 to M-1) of wrdtype;
signal REG: regtype;
signal RW: std_logic_vector(1 downto 0);
begin
...
process(...)
begin
....
for j in 0 to M-1 loop
line 32: REG(j) <= (REG(j)'range => '0');
end loop;
....
end process;
...
end rtl.
when compiler, i see error:
Error: line 32: Unsupported feature error: aggregates are supported only types that map to an array of bits.
this my files:
.....
architecture rtl of sys is
type regtype is array(0 to M-1) of wrdtype;
signal REG: regtype;
signal RW: std_logic_vector(1 downto 0);
begin
...
process(...)
begin
....
for j in 0 to M-1 loop
line 32: REG(j) <= (REG(j)'range => '0');
end loop;
....
end process;
...
end rtl.
when compiler, i see error:
Error: line 32: Unsupported feature error: aggregates are supported only types that map to an array of bits.
this my files: