Error in simulating a gate-level netlist in Modelsim

[shaival132]

Hello friends,

I have RTL design with me which I have synthesized using DC and created gate-level netlist. I have to simulate this gate-level netlist with the cell library and testbench in Modelsim. The issue is I only have a.lib file with me and not a .vhd file of library with me .

I did the following in Library compiler

read_lib saed90nm_typ.lib(this will create saed90nm_typ.db)
write_lib –f vhdl –o saed90nm_typ.vhd (the .vhd will be use by Modelsim)

The write_lib command generates 3 different .vhd files 1] saed90nm_typ_vtables.vhd 2] saed90nm_typ_components.vhd 3] saed90nm_typ_VITAL.vhd for me. I tried using all 3 of them but I am unable to simulate my gate-level netlist with those files as they are throwing errors .

Can any1 help me solving this problem ?
Also if possible can any one attach saed90nm_typ.vhd file here, I am asking as I am assuming its a fairly commonly used library , that will be a great help .

Thanks in advance !

 

[ljxpjpjljx]

you should have the vhd file for gate level simulation , not using write_lib command to generate the code!

 

[rca]

dc will provide the netlist in verilog format (more usual) and you used the verilog description of the std cell as well to execute the simulation.
but you should also add the sdf or be carefull of the delta delay during the simulation....