error in sample hold circuit

[sj_helen]

sample hold circuit

I designed a opamp, which is used in the basic Sampel&Hold circuit.
who can help solve this problem?

ctrl1 for Sample Phase, ctrl2 for Hold Phase

The circuit will finish the sample and hold function by switching capacitors.
There are only 2 capacitors in the SH circuits. They are the two differential Sampling Capacitors which are connected to the differential inputs of opamp respectively.
In the Sample Phase, opamp's inputs are shorted and connected to Vcm. opamp's outputs are also shorted, but not connected to Vcm. Two capacitors are sampling differential input signals respectively.
In the Hold Phase, opamp's inputs and outputs are open circuits. Then the "signal" sides of capacitors are connected to opamp's outputs at the same side.

Theoretically, in the Hold Phase, opamp's inputs should be "Virtual Ground" with voltage value equals to Vcm. and the voltages at the differential outputs should be exactly the same as differential inputs.
Now comes two problems:
1,In the Hold Phase, voltage value of opamp's inputs are not Vcm, and a little higher than Vcm.
So how does this happened? and how to deal with this problem?
2,After Sampling and Hold for the first signal, when in the Sample Phase for the second signal, the opamp's outputs should be shorted and the voltage value should be Vcm.
However, simulation results did not prove this. The simulation shows if the already finished first signal is at the highest input signal level, then in the second Sample Phase, ouput voltage level is higher than Vcm; Whereas, if the finnished first siganl at the lowest value, the output level is lower than Vcm.
how does this happened? and how to deal with this problem?

Thanks a lot.

 

[LvW]

how does a sample and hold circuit function?

It would be very helpful (and much more easier to answer) if you could provide a circuit diagram.
Regards LvW

 

[sj_helen]

errors in sample and hold circuits

to LvW,

Thanks for your advice.
I have already added a plot to illustrate the SH circuit.

 

[LvW]

sample and hold circuit with differential inputs

I have seen, up to now, several different S&H stages with S/C units, however, your circuit is new to me. Therefore my question: From where originates your circuitry ?
Are you sure that it should work as it is ? May be I am wrong, but I miss the unity gain configuration in the hold mode.

 

[sj_helen]

sample hold simulation

I have seen, up to now, several different S&H stages with S/C units, however, your circuit is new to me. Therefore my question: From where originates your circuitry ?
Are you sure that it should work as it is ? May be I am wrong, but I miss the unity gain configuration in the hold mode.

Hi,LvM, thanks for help.

There's a mistake in the former plot, i have corrected it already.

The S/H cirtuit I used is from a paper named ''A 1.0V 40mW 10b 100MS/s Pipeline ADC in 90nm CMOS'', with author Hirotomo Ishii, Ken Tanabe, Tetsuya Iida.

LvM suggests structure from Razavi, but I think, since these Japanese guys had already used this S/H circuit in their pipeline ADC, this S/H circuit should work correctly.

With the corrected plot, i think you can find the unity gain configuration in the hold mode.

and do you think the structure is correct?

 

[jnuhope]

sample hold circuit opamp

I designed a opamp, which is used in the basic Sampel&Hold circuit.
who can help solve this problem?

ctrl1 for Sample Phase, ctrl2 for Hold Phase

The circuit will finish the sample and hold function by switching capacitors.
There are only 2 capacitors in the SH circuits. They are the two differential Sampling Capacitors which are connected to the differential inputs of opamp respectively.
In the Sample Phase, opamp's inputs are shorted and connected to Vcm. opamp's outputs are also shorted, but not connected to Vcm. Two capacitors are sampling differential input signals respectively.
In the Hold Phase, opamp's inputs and outputs are open circuits. Then the "signal" sides of capacitors are connected to opamp's outputs at the same side.

Theoretically, in the Hold Phase, opamp's inputs should be "Virtual Ground" with voltage value equals to Vcm. and the voltages at the differential outputs should be exactly the same as differential inputs.
Now comes two problems:
1,In the Hold Phase, voltage value of opamp's inputs are not Vcm, and a little higher than Vcm.

-- Could it be charge injection? If you vary SW's size or increase CK's voltage, does the input voltage vary as well?

2,After Sampling and Hold for the first signal, when in the Sample Phase for the second signal, the opamp's outputs should be shorted and the voltage value should be Vcm.
However, simulation results did not prove this.

-- Do you need to use this output voltage at samplinig phase? Do you use ideal ota to simulate or non-ideal ota? At sampling phase, ota's input is shorted to vcm and output is shorted together. If your cmfb is fast and resonable gain, it shouldn't be too far from vcm.

Thanks a lot.

Added after 9 minutes:

I have seen, up to now, several different S&H stages with S/C units, however, your circuit is new to me. Therefore my question: From where originates your circuitry ?
Are you sure that it should work as it is ? May be I am wrong, but I miss the unity gain configuration in the hold mode.

I also have seen similar structure in this year's ISSCC paper from Koren authors (sorry I don't have the digest now). It doesn't wast the charge from the input and can run at very high speed. The cons are you can not use bottom plate sampling in this case. The paper also mentioned about some calibaration schemes.

 

[FvM]

Very basically, the device is said to be an opamp. If so, it should neither have a short switch across the output nor be shorted against the source. The situation may be different e.g. for an OTA and a current source as input signal. I hope, that the said paper is able to clarify the circuit operation so far, the present contribution obviously can't.

P.S.: II just noticed, that the original circuit has been edited in the meantime, so the source isn't shorted any more. But the output still is.

B.T.W.: Should all participants of the discussion edit there postings in return? It's near to faking a discussion, to my opinion. Why don't you just show the corrected circuit, keeping the original as well.