error in nested procedure

[manasic]

hello friends;

I have a package. Current declaration of package consist of 1 function and 1 procedure. I did lots of reading online regarding ; a function call in a procedure. However, could not get any clue. I get error stating "output cannot be read".

I might be wrong with the way function is declared. I am using Modelsim.

Can anyone help me. Following is the code and the error message:

Coding language: vhdl

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
-- =============================================================================
package pack1 is
  
  function digit_match(digit : std_logic_vector(3 downto 0)) return integer;
                                                                                                       -- converting the BCD adress to integer
  procedure bcd_conv (signal add1 : in std_logic_vector(12 downto 0);
                      signal digit : out integer;                                                      -- final value
                      signal i1 : out integer;                                                         -- hundredth digit
                      signal i2 : out integer;                                                         -- tenth digit
                      signal i3 : out integer);                                                        -- ones digit
end package pack1;
-- =============================================================================

-- =============================================================================
package body pack1 is
-- =============================================================================
procedure bcd_conv (signal add1 : in std_logic_vector(12 downto 0);signal digit : out integer;signal i1 : out integer;signal i2 : out integer;signal i3 : out integer)                                                                                        
is 
variable d1 : std_logic_vector(3 downto 0) := "0000";                         -- internal varaible to get the digit
variable d2 : std_logic_vector(3 downto 0) := "0000";                         -- internal varaible 2 for the digit
variable d3 : std_logic_vector(3 downto 0) := "0000";                         -- internal varaible 3 for the digit
 begin                                
  d1(3) := add1(0);
  d1(2) := add1(1);
  d1(1) := add1(2);
  d1(0) := add1(3);

  d2(3) := add1(4);
  d2(2) := add1(5);
  d2(1) := add1(6);
  d2(0) := add1(7);

  d3(3) := add1(8);
  d3(2) := add1(9);
  d3(1) := add1(10);
  d3(0) := add1(11);

  i1 <= digit_match(d1);
  i2 <= digit_match(d2);
  i3 <= digit_match(d3);

  digit <= (i1*100) + (i2*10) + (i3);

end bcd_conv;
-- =============================================================================
-- =============================================================================
function digit_match(digit : std_logic_vector(3 downto 0)) return integer is                   -- getting corresponding integers
variable d1 : integer := 0;
                                                        
begin
  case digit is
    when "0000" => 
          d1 := 0;
    when "0001" => 
          d1 := 1;
    when "0010" => 
          d1 := 2;
    when "0011" => 
          d1 := 3;
    when "0100" => 
          d1 := 4;
    when "0101" => 
          d1 := 5;
    when "0110" => 
          d1 := 6;
    when "0111" => 
          d1 := 7;
    when "1000" => 
          d1 := 8;
    when "1001" =>
         d1 := 9;
    when others => null;
     end case;
     return d1;
end function digit_match;
-- =============================================================================
end pack1;

error message:

Error: C:/Modeltech_pe_edu_10.2b/examples/pack1.vhd(45): Cannot read output "i3".
VHDL 2008 allows reading outputs.
This facility is enabled by compiling with -2008.
** Error: C:/Modeltech_pe_edu_10.2b/examples/pack1.vhd(45): Cannot read output "i1".
VHDL 2008 allows reading outputs.
This facility is enabled by compiling with -2008.
** Error: C:/Modeltech_pe_edu_10.2b/examples/pack1.vhd(45): Cannot read output "i2".
VHDL 2008 allows reading outputs.
This facility is enabled by compiling with -2008.
** Error: C:/Modeltech_pe_edu_10.2b/examples/pack1.vhd(80): VHDL Compiler exiting

 

[TrickyDicky]

Its a simple rule that applies to procedures and entities. You cannot read anything of mode out. So you need temporary internal versions of i1 i2 and i3.