Error in code project

[bzu]

hello!

i have error in my code ( vhdl )
and i cant ge the right code
please help me !!

module comp(AeqlB,AgrtB,AlessB,A0,A1,B0,B1);

 output AeqlB,AgrtB,AlessB;
 input A0,A1,B0,B1;
 wire A0not,A1not,B0not,B1not,[0:3]E,[0:15]W;

not G1(A0not,A0),
    G2(A1not,A10),
    G3(B0not,B0),
    G4(B1not,B1);

and G5(E[0],A0not,A1not),
    G6(E[1],A0not,A1),
    G7(E[2],A0,A1not),
    G8(E[3],A0,A1);
    
and G9(W[0],B0not,B1not,E[0]),
    G10(W[1],B0not,B1,E[0]),
    G11(W[2],B0,B1not,E[0]),
    G12(W[3],B0,B1,E[0]),
    G13(W[4],B0not,B1not,E[1]),
    G14(W[5],B0not,B1,E[1]),
    G15(W[6],B0,B1not,E[1]),
    G16(W[7],B0,B1,E[1]),
    G17(W[8],B0not,B1not,E[2]),
    G18(W[9],B0not,B1,E[2]),
    G19(W[10],B0,B1not,E[2]),
    G20(W[11],B0,B1,E[2]),
    G21(W[12],B0not,B1not,E[3]),
    G22(W[13],B0not,B1,E[3]),
    G23(W[14],B0,B1not,E[3]),
    G24(W[15],B0,B1,E[3]);
    
or G25(AeqlB,W[0],W[5],W[10],W[15]),
   G26(AgrtB,W[4],W[8],W[9],W[12],W[13],W[14]),
   G27(AlessB,W[1],W[2],W[3],W[6],W[7],W[11]);
   
endmodule

Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
Info: Version 9.0 Build 132 02/25/2009 SJ Web Edition
Info: Processing started: Wed Aug 28 20:35:52 2013
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off comp -c comp
Error (10500): VHDL syntax error at comp.vhd(1) near text "module"; expecting "entity", or "architecture", or "use", or "library", or "package", or "configuration"
Info: Found 0 design units, including 0 entities, in source file comp.vhd
Error (10170): Verilog HDL syntax error at Verilog1.v(5) near text "["; expecting an identifier
Error (10112): Ignored design unit "comp" at Verilog1.v(1) due to previous errors
Info: Found 0 design units, including 0 entities, in source file Verilog1.v
Error: Quartus II Analysis & Synthesis was unsuccessful. 3 errors, 0 warnings
Error: Peak virtual memory: 241 megabytes
Error: Processing ended: Wed Aug 28 20:35:52 2013
Error: Elapsed time: 00:00:00
Error: Total CPU time (on all processors): 00:00:01

 

[mrflibble]

I suggest giving your spacebar more love.

You have:

wire A0not,A1not,B0not,B1not,[0:3]E,[0:15]W;

Change it to:

wire A0not, A1not, B0not, B1not, [0:3] E, [0:15] W;

I also suggest reading error messages.

Error (10170): Verilog HDL syntax error at Verilog1.v(5) near text "["; expecting an identifier[/]

Which tells you "go read line 5 of your code. gogogo!" Guess which line number the above code change just fixed. I'll give you 5 guesses.

 

[FvM]

Error (10500): VHDL syntax error at comp.vhd(1) near text "module"; expecting "entity", or "architecture", or "use", or "library", or "package", or "configuration"

You are apparently elaborating Verilog code in a VHDL file.

Error (10170): Verilog HDL syntax error at Verilog1.v(5) near text "["; expecting an identifier

Verilog syntax error in wire definition. (vector range belongs to the type, not the variable/wire name.)

wire A0not, A1not, B0not, B1not;
wire [0:3] E;
wire [0:15] W;

 

[mrflibble]

Well damn. You're right and I'm wrong.

I thought the whitespace between range and identifier was mandatory ... turns out it isn't.

wire [0:3]E; is just as legal as wire[0:3]E;

That and I was mixing up something about ranges and declaring mutiple wires/regs with one statement. I did remember to never do a one-liner like the above (as in always get legal code on autopilot), but didn't remember it was actually illegal to use a range on the 2nd-Nth identifier in a wire/reg statement. Pesky unreliable brain. :-/

 

[bzu]

thaaaaaaaaaanks all
all thing is good now and the code wrok well !
the error in the vector change to W0,W1.... this the correct

thanks mrflibble thanks FvM