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error for 64 bit ripple carry adder

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Mahammad

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Code Verilog - [expand]
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module rippl(
    input [63:0] a,
    input [63:0] b,
    input cin,
    output [63:0] s,
    output cout
    );
wire temp[63:0];
assign temp[0]=cin;
genvar i;
always @(*)
for(i=0;i<64;i=i+1)
begin
s[i]<=(a[i]^(b[i]^temp[i]));
temp[i+1]<=(((a[i]&b[i])|(b[i]&temp[i]))|(temp[i]&a[i]));
end
 
assign cout=temp[63];
end
 
endmodule

 
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std_match

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You will avoid a lot of problems if you use blocking assignments "=" in combinatorial always blocks and non-blocking assignments "<=" in clocked always blocks until you understand when to break this rule.
 

fouwad

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what exactly is the error, need some explanation
 

vGoodtimes

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temp is too small. The generate will assign to temp[63+1].
 

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temp is too small. The generate will assign to temp[63+1].

besides that, it should be doing the following assign for cout to get the carry output of the add.

Code:
assign cout = temp[64];
 

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