Mahammad
Member level 3

Code Verilog - [expand] 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 module rippl( input [63:0] a, input [63:0] b, input cin, output [63:0] s, output cout ); wire temp[63:0]; assign temp[0]=cin; genvar i; always @(*) for(i=0;i<64;i=i+1) begin s[i]<=(a[i]^(b[i]^temp[i])); temp[i+1]<=(((a[i]&b[i])|(b[i]&temp[i]))|(temp[i]&a[i])); end assign cout=temp[63]; end endmodule
Last edited by a moderator: