gani
Newbie level 6
to_unsigned
hi all
can anybody help me out with this code..
i generated the below code using matlab..i'm able to simulate this code using modelsim...but when i'm trying synthesizing the same code using xilinx its giving some errors....or can anyone plz convert this code to verilog...
thanx in advance
LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
USE IEEE.numeric_std.ALL;
ENTITY poly_int IS
PORT( clk : IN std_logic;
clk_enable : IN std_logic;
reset : IN std_logic;
filter_in : IN real; -- double
filter_out : OUT real; -- double
ce_out : OUT std_logic
);
END poly_int;
ARCHITECTURE rtl OF poly_int IS
-- Local Functions
-- Type Definitions
TYPE delay_pipeline_type IS ARRAY (NATURAL range <>) OF real; -- double
-- Constants
CONSTANT coeffphase1_1 : real := 2.5000000000000000E-001; -- double
CONSTANT coeffphase1_2 : real := 7.5000000000000000E-001; -- double
CONSTANT coeffphase2_1 : real := 5.0000000000000000E-001; -- double
CONSTANT coeffphase2_2 : real := 5.0000000000000000E-001; -- double
CONSTANT coeffphase3_1 : real := 7.5000000000000000E-001; -- double
CONSTANT coeffphase3_2 : real := 2.5000000000000000E-001; -- double
CONSTANT coeffphase4_1 : real := 1.0000000000000000E+000; -- double
CONSTANT coeffphase4_2 : real := 0.0000000000000000E+000; -- double
-- Signals
SIGNAL cur_count : unsigned(1 DOWNTO 0); -- ufix2
SIGNAL phase_3 : std_logic; -- boolean
SIGNAL ce_out_reg : std_logic; -- boolean
SIGNAL delay_pipeline : delay_pipeline_type(0 TO 1) := (0.0, 0.0); -- double
SIGNAL product : real := 0.0; -- double
SIGNAL product_mux : real := 0.0; -- double
SIGNAL product_1 : real := 0.0; -- double
SIGNAL product_mux_1 : real := 0.0; -- double
SIGNAL sum1 : real := 0.0; -- double
SIGNAL output_register : real := 0.0; -- double
BEGIN
ce_output : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
cur_count <= to_unsigned(0, 2);
ELSIF clk'event AND clk = '1' THEN
IF clk_enable = '1' THEN
IF cur_count = to_unsigned(3, 2) THEN
cur_count <= to_unsigned(0, 2);
ELSE
cur_count <= cur_count + 1;
END IF;
END IF;
END IF;
END PROCESS ce_output;
phase_3 <= '1' WHEN cur_count = to_unsigned(3, 2) AND clk_enable = '1' ELSE '0';
-- ------------------ CE Output Register ------------------
ce_output_register : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
ce_out_reg <= '0';
ELSIF clk'event AND clk = '1' THEN
ce_out_reg <= phase_3;
END IF;
END PROCESS ce_output_register;
-- ---------------- Delay Registers ----------------
Delay_Pipeline_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
delay_pipeline(0 TO 1) <= (OTHERS => 0.0000000000000000E+000);
ELSIF clk'event AND clk = '1' THEN
IF phase_3 = '1' THEN
delay_pipeline(0) <= filter_in;
delay_pipeline(1) <= delay_pipeline(0);
END IF;
END IF;
END PROCESS Delay_Pipeline_process;
product_mux <= coeffphase1_2 WHEN ( cur_count=to_unsigned(0, 2) ) ELSE
coeffphase2_2 WHEN ( cur_count=to_unsigned(1, 2) ) ELSE
coeffphase3_2 WHEN ( cur_count=to_unsigned(2, 2) ) ELSE
coeffphase4_2;
product <= delay_pipeline(1) * product_mux;
product_mux_1 <= coeffphase1_1 WHEN ( cur_count=to_unsigned(0, 2) ) ELSE
coeffphase2_1 WHEN ( cur_count=to_unsigned(1, 2) ) ELSE
coeffphase3_1 WHEN ( cur_count=to_unsigned(2, 2) ) ELSE
coeffphase4_1;
product_1 <= delay_pipeline(0) * product_mux_1;
sum1 <= product_1 + product;
Output_Register_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
output_register <= 0.0000000000000000E+000;
ELSIF clk'event AND clk = '1' THEN
IF clk_enable = '1' THEN
output_register <= sum1;
END IF;
END IF;
END PROCESS Output_Register_process;
-- Assignment Statements
ce_out <= ce_out_reg;
filter_out <= output_register;
END rtl;
hi all
can anybody help me out with this code..
i generated the below code using matlab..i'm able to simulate this code using modelsim...but when i'm trying synthesizing the same code using xilinx its giving some errors....or can anyone plz convert this code to verilog...
thanx in advance
LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
USE IEEE.numeric_std.ALL;
ENTITY poly_int IS
PORT( clk : IN std_logic;
clk_enable : IN std_logic;
reset : IN std_logic;
filter_in : IN real; -- double
filter_out : OUT real; -- double
ce_out : OUT std_logic
);
END poly_int;
ARCHITECTURE rtl OF poly_int IS
-- Local Functions
-- Type Definitions
TYPE delay_pipeline_type IS ARRAY (NATURAL range <>) OF real; -- double
-- Constants
CONSTANT coeffphase1_1 : real := 2.5000000000000000E-001; -- double
CONSTANT coeffphase1_2 : real := 7.5000000000000000E-001; -- double
CONSTANT coeffphase2_1 : real := 5.0000000000000000E-001; -- double
CONSTANT coeffphase2_2 : real := 5.0000000000000000E-001; -- double
CONSTANT coeffphase3_1 : real := 7.5000000000000000E-001; -- double
CONSTANT coeffphase3_2 : real := 2.5000000000000000E-001; -- double
CONSTANT coeffphase4_1 : real := 1.0000000000000000E+000; -- double
CONSTANT coeffphase4_2 : real := 0.0000000000000000E+000; -- double
-- Signals
SIGNAL cur_count : unsigned(1 DOWNTO 0); -- ufix2
SIGNAL phase_3 : std_logic; -- boolean
SIGNAL ce_out_reg : std_logic; -- boolean
SIGNAL delay_pipeline : delay_pipeline_type(0 TO 1) := (0.0, 0.0); -- double
SIGNAL product : real := 0.0; -- double
SIGNAL product_mux : real := 0.0; -- double
SIGNAL product_1 : real := 0.0; -- double
SIGNAL product_mux_1 : real := 0.0; -- double
SIGNAL sum1 : real := 0.0; -- double
SIGNAL output_register : real := 0.0; -- double
BEGIN
ce_output : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
cur_count <= to_unsigned(0, 2);
ELSIF clk'event AND clk = '1' THEN
IF clk_enable = '1' THEN
IF cur_count = to_unsigned(3, 2) THEN
cur_count <= to_unsigned(0, 2);
ELSE
cur_count <= cur_count + 1;
END IF;
END IF;
END IF;
END PROCESS ce_output;
phase_3 <= '1' WHEN cur_count = to_unsigned(3, 2) AND clk_enable = '1' ELSE '0';
-- ------------------ CE Output Register ------------------
ce_output_register : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
ce_out_reg <= '0';
ELSIF clk'event AND clk = '1' THEN
ce_out_reg <= phase_3;
END IF;
END PROCESS ce_output_register;
-- ---------------- Delay Registers ----------------
Delay_Pipeline_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
delay_pipeline(0 TO 1) <= (OTHERS => 0.0000000000000000E+000);
ELSIF clk'event AND clk = '1' THEN
IF phase_3 = '1' THEN
delay_pipeline(0) <= filter_in;
delay_pipeline(1) <= delay_pipeline(0);
END IF;
END IF;
END PROCESS Delay_Pipeline_process;
product_mux <= coeffphase1_2 WHEN ( cur_count=to_unsigned(0, 2) ) ELSE
coeffphase2_2 WHEN ( cur_count=to_unsigned(1, 2) ) ELSE
coeffphase3_2 WHEN ( cur_count=to_unsigned(2, 2) ) ELSE
coeffphase4_2;
product <= delay_pipeline(1) * product_mux;
product_mux_1 <= coeffphase1_1 WHEN ( cur_count=to_unsigned(0, 2) ) ELSE
coeffphase2_1 WHEN ( cur_count=to_unsigned(1, 2) ) ELSE
coeffphase3_1 WHEN ( cur_count=to_unsigned(2, 2) ) ELSE
coeffphase4_1;
product_1 <= delay_pipeline(0) * product_mux_1;
sum1 <= product_1 + product;
Output_Register_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
output_register <= 0.0000000000000000E+000;
ELSIF clk'event AND clk = '1' THEN
IF clk_enable = '1' THEN
output_register <= sum1;
END IF;
END IF;
END PROCESS Output_Register_process;
-- Assignment Statements
ce_out <= ce_out_reg;
filter_out <= output_register;
END rtl;