error and warning in vhdl in counter

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-- Company: 
-- Engineer: 
-- 
-- Create Date:    14:30:01 05/25/2015 
-- Design Name: 
-- Module Name:    count - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity count is
    Port ( 
	        reset : in  STD_LOGIC;
           output : out  STD_LOGIC_vector (1 downto 0);
			  clk : in  STD_LOGIC);
end count;

architecture Behavioral of count is

begin


process (clk,reset)

variable y: STD_LOGIC_vector (1 downto 0):= "00";


begin


 
 
 
 
 
if (reset ='0') then 
if (rising_edge(clk)) then


y := y+"01";




else

 end if ;
 
 output (1 downto 0) <= y (1 downto 0);

 
else 
output (1 downto 0) <= "00"; 




end if;
 



end process;
end Behavioral;

If reset then
     --do something
elsif rising_edge(clk) then
--do something else
Endif;

library IEEE;
        
            use ieee.std_logic_1164.all;
        
            use ieee.std_logic_unsigned.all;
        
            entity counter is 
        
             port(Clock, CLR : in  std_logic;
        
             Q : out std_logic_vector(3 downto 0));
        
             end counter;
        
             architecture archi of counter is  
        
             signal tmp: std_logic_vector(3 downto 0);
        
             begin
        
             process (Clock, CLR) 
        
             begin   
        
                   if (CLR='1') then   
        
                          tmp <= "0000";  
        
                   elsif (Clock'event and Clock='1') then 
        
                          tmp <= tmp + 1;
        
                   end if;     
        
             end process; 
        
                   Q <= tmp;
        
             end archi;