error and warning in vhdl in counter

[p11]

---------------------------------------------------------------------------------
-- Company: 
-- Engineer: 
-- 
-- Create Date:    14:30:01 05/25/2015 
-- Design Name: 
-- Module Name:    count - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity count is
    Port ( 
	        reset : in  STD_LOGIC;
           output : out  STD_LOGIC_vector (1 downto 0);
			  clk : in  STD_LOGIC);
end count;

architecture Behavioral of count is

begin


process (clk,reset)

variable y: STD_LOGIC_vector (1 downto 0):= "00";


begin


 
 
 
 
 
if (reset ='0') then 
if (rising_edge(clk)) then


y := y+"01";




else

 end if ;
 
 output (1 downto 0) <= y (1 downto 0);

 
else 
output (1 downto 0) <= "00"; 




end if;
 



end process;
end Behavioral;

WARNING:Security:42 - Your software subscription period has lapsed. Your current
WARNING:Security:42 - Your software subscription period has lapsed. Your current version of Xilinx tools will continue
WARNINGar:100 - Design is not completely routed. There are 8 signals that are not
completely routed in this design. See the "count.unroutes" file for a list of
all unrouted signals. Check for other warnings in your PAR report that might
indicate why these nets are unroutable. These nets can also be evaluated
in FPGA Editor by selecting "Unrouted Nets" in the List Window.
WARNINGrojectMgmt - File D:/VHDL_14.4/lcd1/lcd1.stx is missing.

this is a design of a 2 bit counter . the test bench waveform is absoluytely correct but , cant implement the design. i think i should not have initiated the variable value with 00, as its unnecessary , but still cant understand the reason behind this warning.

 

[barry]

You don't want your clock statement inside the "if reset" statement. It should be of the form

If reset then
     --do something
elsif rising_edge(clk) then
--do something else
Endif;

Also, I'm not sure what your intent for that if reset statement is supposed to do.

 

[TrickyDicky]

I guess you still didnt read a text book or tutorial, as a counter is one of the first basic exercises/examples.

 

[p11]

library IEEE;
        
            use ieee.std_logic_1164.all;
        
            use ieee.std_logic_unsigned.all;
        
            entity counter is 
        
             port(Clock, CLR : in  std_logic;
        
             Q : out std_logic_vector(3 downto 0));
        
             end counter;
        
             architecture archi of counter is  
        
             signal tmp: std_logic_vector(3 downto 0);
        
             begin
        
             process (Clock, CLR) 
        
             begin   
        
                   if (CLR='1') then   
        
                          tmp <= "0000";  
        
                   elsif (Clock'event and Clock='1') then 
        
                          tmp <= tmp + 1;
        
                   end if;     
        
             end process; 
        
                   Q <= tmp;
        
             end archi;

this is a program from a tutorial, of a 4 bit counter. its also showing ,

WARNINGar:100 - Design is not completely routed. There are 6 signals that are not
completely routed in this design. See the "count.unroutes" file for a list of
all unrouted signals. Check for other warnings in your PAR report that might
indicate why these nets are unroutable. These nets can also be evaluated
in FPGA Editor by selecting "Unrouted Nets" in the List Window.
WARNINGrojectMgmt - File D:/VHDL_14.4/lcd1/lcd1.stx is missing.

 

[barry]

I think there might be something wrong with your Xilinx setup. There's a missing file and some lapsed software issues.