HiBlackuni said:I like have Vds as one more design constrain, becoz it determines the voltage headroom/swing. so i like to have its relation with w/l
HiBlackuni said:Hi hr_rezaee,
Please point me the mistake i m doing!
Here are the points i like to know
1. If i have two transistors stacked(as the example i pasted earlier) how the VDS of the m3 and m4 is arrived at? Because if i like to keep the node n1 at vdd/2 then how can i achive it? I am able to do that by iterative SPICE simulations But i believe there should be some sort of mathematical relation.
If the design headroom is 1v then 100mv difference is a great number.
Sorry for asking such a simple Question but i don't have an ans for this so upto me its tough Q
Thanks,
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