")" is lacking.suling said:veriloga.va, line 28: "(V(en[1] == V(vdd12)) && (V(en[0]) == V(vdd12)))<<--?"
"in" is bus.suling said:veriloga.va, line 36: "V(out) <+ V(in)<<--? *c;"
No. Both "in" and "en" are bus in your declaration.suling said:As seen in the declaration, "in" is an input, en is then the bus.
input [1:0] en, in;
electrical [1:0] en, in;
"(" is missing.suling said:Code:(V(en[1]) == V(vdd12)) && (V(en[0]) == V(vdd12)))
I think you will make very easy mistakes even in Verilog-AMS or Verilog-D.suling said:As I am new to this, sometimes I feel quite confusing on the syntax and limitation by veriloga as comapred to verilogams.
Error messages from simulator are very clear to undesrtand errors in your code.suling said:Is there ways/helps that I can refer to check thru the code with description of errors clearly.
You must not put ";" in the end of line.suling said:module a (vdd12, gnd, en, in, out);
`define Nbits 2;
I can't understand what you want to mean.suling said:Hi, can we have several assign variables within a case or if else statement?
Is there any skip statement in veriloga?
It has to be:suling said:veriloga.va, line 47: "0: gain = 39; nf = 2.37; <<--? "
veriloga.va, line 47: Error: syntax error
suling said:s21 = -`db20_real(gain);
rnf = `db10_real(nf);
noise_current = 2*sqrt((rnf-1)*1.380620e-23*$temperature/rin);
No one except for you have such confusion.suling said:really confusing, do not know if which document to follow.
Document which you attached is "Training Manual".suling said:Had tried to follow close to the examples in the attached lecture notes below, don't see begin in case.
We use cookies and similar technologies for the following purposes:
Do you accept cookies and these technologies?
We use cookies and similar technologies for the following purposes:
Do you accept cookies and these technologies?